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PCA9555N PDF预览

PCA9555N

更新时间： 2024-02-12 06:17:58
品牌 Logo 应用领域
恩智浦 - NXP 并行IO端口微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
22页 185K
描述
16-bit I2C and SMBus I/O port with interrupt

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PCA9555N 技术参数

生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN, LCC24/28,.14X.2,20针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.69
Is Samacsys：N最大时钟频率：0.4 MHz
JESD-30 代码：R-PQCC-N24长度：5.5 mm
位数：16I/O 线路数量：16
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装等效代码：LCC24/28,.14X.2,20封装形状：RECTANGULAR
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE电源：2.5/5 V
认证状态：Not Qualified座面最大高度：1 mm
子类别：Parallel IO Ports最大压摆率：0.2 mA
最大供电电压：5.5 V最小供电电压：2.3 V
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD宽度：3.5 mm
uPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches：1

PCA9555N 数据手册

 浏览型号PCA9555N的Datasheet PDF文件第3页浏览型号PCA9555N的Datasheet PDF文件第4页浏览型号PCA9555N的Datasheet PDF文件第5页浏览型号PCA9555N的Datasheet PDF文件第7页浏览型号PCA9555N的Datasheet PDF文件第8页浏览型号PCA9555N的Datasheet PDF文件第9页 
Philips Semiconductors  
Product data sheet  
16-bit I2C and SMBus I/O port with interrupt  
PCA9555  
REGISTERS  
Registers 4 and 5 — Polarity Inversion Registers  
bit  
N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0  
Command Byte  
default  
bit  
0
0
0
0
0
0
0
0
Command  
Register  
N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0  
0
1
2
3
4
5
6
7
Input port 0  
default  
0
0
0
0
0
0
0
0
Input port 1  
This register allows the user to invert the polarity of the Input Port  
register data. If a bit in this register is set (written with ‘1’), the Input  
Port data polarity is inverted. If a bit in this register is cleared (written  
with a ‘0’), the Input Port data polarity is retained.  
Output port 0  
Output port 1  
Polarity inversion port 0  
Polarity inversion port 1  
Configuration port 0  
Configuration port 1  
Registers 6 and 7 — Configuration Registers  
bit  
C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0  
default  
bit  
1
1
1
1
1
1
1
1
The command byte is the first byte to follow the address byte during  
a write transmission. It is used as a pointer to determine which of the  
following registers will be written or read.  
C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0  
default  
1
1
1
1
1
1
1
1
This register configures the directions of the I/O pins. If a bit in this  
register is set (written with ‘1’), the corresponding port pin is enabled  
as an input with high impedance output driver. If a bit in this register  
is cleared (written with ‘0’), the corresponding port pin is enabled as  
Registers 0 and 1 — Input Port Registers  
bit  
I0.7  
X
I0.6  
X
I0.5  
X
I0.4  
X
I0.3  
X
I0.2  
X
I0.1 IO.0  
default  
bit  
X
I1.1  
X
X
I1.0  
X
an output. Note that there is a high value resistor tied to V at each  
DD  
pin. At reset the device’s ports are inputs with a pull-up to V  
.
I1.7  
X
I1.6  
X
I1.5  
X
I1.4  
X
I1.3  
X
I1.2  
X
DD  
default  
This register is an input-only port. It reflects the incoming logic levels  
of the pins, regardless of whether the pin is defined as an input or an  
output by Register 3. Writes to this register have no effect.  
POWER-ON RESET  
When power is applied to V , an internal power-on reset holds the  
DD  
PCA9555 in a reset condition until V has reached V  
. At that  
DD  
POR  
point, the reset condition is released and the PCA9555 registers and  
SMBus state machine will initialize to their default states. The  
power-on reset typically completes the reset and enables the part by  
The default value ‘X’ is determined by the externally applied logic  
level.  
the time the power supply is above V  
. However, when it is  
POR  
Registers 2 and 3 — Output Port Registers  
required to reset the part by lowering the power supply, it is  
necessary to lower it below 0.2 V.  
bit  
O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0  
default  
bit  
1
1
1
1
1
1
1
1
O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0  
default  
1
1
1
1
1
1
1
1
This register is an output-only port. It reflects the outgoing logic  
levels of the pins defined as outputs by Register 6 and 7. Bit values  
in this register have no effect on pins defined as inputs. In turn,  
reads from this register reflect the value that is in the flip-flop  
controlling the output selection, NOT the actual pin value.  
6
2004 Sep 30  
1...3456789...22

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