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PCA9538PW/Q900,118 PDF预览

PCA9538PW/Q900,118

更新时间: 2024-02-12 15:48:35
品牌 Logo 应用领域
恩智浦 - NXP PC光电二极管外围集成电路
页数 文件大小 规格书
34页 450K
描述
PCA9538 - 8-bit I²C-bus and SMBus low power I/O port with interrupt and reset TSSOP 16-Pin

PCA9538PW/Q900,118 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:TSSOP包装说明:TSSOP,
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:1.73
JESD-30 代码:R-PDSO-G16长度:5 mm
湿度敏感等级:1I/O 线路数量:8
端口数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED筛选级别:AEC-Q100
座面最大高度:1.1 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

PCA9538PW/Q900,118 数据手册

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PCA9538  
NXP Semiconductors  
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset  
6.6 I/O port  
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a  
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.  
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the  
state of the Output Port register. Care should be exercised if an external voltage is applied  
to an I/O configured as an output because of the low-impedance paths that exist between  
the pin and either VDD or VSS  
.
data from  
shift register  
configuration  
register  
output port  
register data  
V
DD  
data from  
shift register  
Q1  
D
Q
FF  
write  
configuration  
pulse  
D
Q
CK  
Q
FF  
I/O pin  
Q2  
write pulse  
CK  
V
input port  
register  
SS  
output port  
register  
D
Q
input port  
register data  
FF  
read pulse  
CK  
to INT  
polarity inversion  
register  
data from  
shift register  
polarity  
inversion  
register data  
D
Q
FF  
write polarity  
pulse  
CK  
002aad723  
Remark: At power-on reset, all registers return to default values.  
Fig 6. Simplified schematic of IO0 to IO7  
PCA9538  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2017. All rights reserved.  
Product data sheet  
Rev. 8 — 8 November 2017  
9 of 34  
 

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