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PCA9538DGVRG4

更新时间： 2024-01-30 06:00:01
品牌 Logo 应用领域
德州仪器 - TI 并行IO端口微控制器和处理器外围集成电路电视光电二极管输出元件
页数 文件大小 规格书
29页 480K
描述
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

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PCA9538DGVRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：GREEN, PLASTIC, TVSOP-16针数：16
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.58
Is Samacsys：NJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：3.6 mm
湿度敏感等级：1位数：8
I/O 线路数量：8端口数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25,16
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：2.5/5 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Parallel IO Ports最大供电电压：5.5 V
最小供电电压：2.3 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmuPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches：1

PCA9538DGVRG4 数据手册

 浏览型号PCA9538DGVRG4的Datasheet PDF文件第1页浏览型号PCA9538DGVRG4的Datasheet PDF文件第2页浏览型号PCA9538DGVRG4的Datasheet PDF文件第3页浏览型号PCA9538DGVRG4的Datasheet PDF文件第5页浏览型号PCA9538DGVRG4的Datasheet PDF文件第6页浏览型号PCA9538DGVRG4的Datasheet PDF文件第7页 
PCA9538  
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER  
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS  
www.ti.com  
SCPS126D–SEPTEMBER 2006–REVISED MARCH 2007  
SIMPLIFIED SCHEMATIC OF P0 TO P7  
Data From  
Shift Register  
Configuration  
Output Port  
Register Data  
Register  
V
CC  
Data From  
Shift Register  
Q1  
D
Q
FF  
K
Write Configuration  
Pulse  
D
C
Q
Q
C
Q
FF  
K
P0 to P7  
Write Pulse  
ESD Protection  
Diode  
Q2  
Output Port  
Register  
Input Port  
Register  
GND  
Input Port  
Register Data  
D
Q
FF  
K
Read Pulse  
C
Q
To INT  
Data From  
Shift Register  
Polarity  
Register Data  
D
C
Q
Q
FF  
K
Write Polarity  
Pulse  
Polarity  
Inversion  
Register  
A. At power-on reset, all registers return to default values.  
I/O Port  
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input  
voltage may be raised above VCC to a maximum of 5.5 V.  
If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In  
this case, there are low impedance paths between the I/O pin and either VCC or GND. The external voltage  
applied to this I/O pin should not exceed the recommended levels for proper operation.  
I2C Interface  
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be  
connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data  
transfer may be initiated only when the bus is not busy.  
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on  
the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address  
byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).  
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA  
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A1) of the slave device  
must not be changed between the Start and the Stop conditions.  
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain  
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control  
commands (Start or Stop) (see Figure 2).  
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the  
master (see Figure 1).  
4
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