Datasheet > 微控制器和处理器 > 并行 IO 端口> PCA9536TK

PCA9536TK

更新时间： 2024-01-05 20:34:54

品牌	Logo	应用领域
恩智浦 - NXP		并行IO端口微控制器和处理器外围集成电路光电二极管
页数	文件大小	规格书
22页	199K
描述
4-bit I2C-bus and SMBus I/O port

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PCA9536TK 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	VFBGA, BGA8,2X4,20	针数：	8
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.71
JESD-30 代码：	R-XBGA-B8	JESD-609代码：	e1
长度：	1.98 mm	湿度敏感等级：	1
位数：	4	I/O 线路数量：	4
端口数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	VFBGA
封装等效代码：	BGA8,2X4,20	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	2.5/5 V	认证状态：	Not Qualified
座面最大高度：	0.5 mm	子类别：	Parallel IO Ports
最大供电电压：	5.5 V	最小供电电压：	2.3 V
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	0.5 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	0.9 mm
uPs/uCs/外围集成电路类型：	PARALLEL IO PORT, GENERAL PURPOSE	Base Number Matches：	1

PCA9536TK 数据手册

PCA9536

NXP Semiconductors

4-bit I²C-bus and SMBus I/O port

6.1.5 Register 3 - Configuration register

This register configures the directions of the I/O pins. If a bit in this register is set, the

corresponding port pin is enabled as an input with high-impedance output driver. If a bit in

this register is cleared, the corresponding port pin is enabled as an output. At reset, the

I/Os are configured as inputs with a weak pull-up to V_DD

‘Not used’ bits can be programmed with either logic 0 or logic 1.

Table 7.

Legend: * default value

Bit

Symbol

Access

R/W

Value

Description

not used

configures the directions of the I/O pins

0 = corresponding port pin enabled as an output

1 = corresponding port pin configured as input

(default value)

6.2 Power-on reset

When power is applied to V_DD, an internal Power-On Reset (POR) holds the PCA9536 in

a reset condition until V_DDhas reached V_POR. At that point, the reset condition is released

and the PCA9536 registers and state machine will initialize to their default states.

Thereafter, V_DDmust be lowered below 0.2 V to reset the device.

For a power reset cycle, V_DDmust be lowered below 0.2 V and then restored to the

operating voltage.

6.3 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a

high-impedance input with a weak pull-up (100 kΩ typical) to V_DD. The input voltage may

be raised above V_DDto a maximum of 5.5 V.

If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the

state of the Output Port register. Care should be exercised if an external voltage is applied

to an I/O configured as an output because of the low-impedance paths that exist between

the pin and either V_DDor V_SS

PCA9536_5

Product data sheet

Rev. 05 — 25 January 2010

6 of 22

1...3 4 567 8 9...22

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与PCA9536TK相关器件

型号	品牌	描述	获取价格	数据表
PCA9536YZPR	TI	REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS	获取价格
PCA9537	NXP	4-bit I2C and SMBus low power I/O port with interrupt and reset	获取价格
PCA9537DP	NXP	4-bit I2C-bus and SMBus low power I/O port with interrupt and reset	获取价格
PCA9537DP.118	NXP	4-bit I2C-bus and SMBus low power I/O port with interrupt and reset	获取价格
PCA9538	TI	REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIG	获取价格
PCA9538	NXP	8-bit I2C and SMBus low power I/O port with interrupt and reset	获取价格

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