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PCA9534PW,112 PDF预览

PCA9534PW,112

更新时间： 2024-01-03 13:21:20
品牌 Logo 应用领域
恩智浦 - NXP PC光电二极管外围集成电路
页数 文件大小 规格书
27页 262K
描述
PCA9534 - 8-bit I2C-bus and SMBus low power I/O port with interrupt TSSOP 16-Pin

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PCA9534PW,112 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP16,.25
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.19
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：5 mm湿度敏感等级：1
位数：8I/O 线路数量：8
端口数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：2.5/5 V认证状态：Not Qualified
座面最大高度：1.1 mm子类别：Parallel IO Port
最大供电电压：5.5 V最小供电电压：2.3 V
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：4.4 mm
uPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches：1

PCA9534PW,112 数据手册

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PCA9534  
NXP Semiconductors  
8-bit I2C-bus and SMBus low power I/O port with interrupt  
6.1.5 Register 3 - Configuration register  
This register configures the directions of the I/O pins. If a bit in this register is set, the  
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in  
this register is cleared, the corresponding port pin is enabled as an output. At reset, the  
I/Os are configured as inputs.  
Table 8.  
Register 3 - Configuration register bit description  
Legend: * default value.  
Bit  
7
Symbol  
C7  
Access  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Value  
1*  
Description  
configures the directions of the I/O pins  
0 = corresponding port pin enabled as an output  
6
C6  
1*  
1 = corresponding port pin configured as input  
(default value)  
5
C5  
1*  
4
C4  
1*  
3
C3  
1*  
2
C2  
1*  
1
C1  
1*  
0
C0  
1*  
6.2 Power-on reset  
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9534 in  
a reset condition until VDD has reached VPOR. At that point, the reset condition is released  
and the PCA9534 registers and state machine will initialize to their default states.  
Thereafter, VDD must be lowered below 0.2 V to reset the device.  
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the  
operating voltage.  
6.3 Interrupt output  
The open-drain interrupt output is activated when one of the port pins change state and  
the pin is configured as an input. The interrupt is deactivated when the input returns to its  
previous state or the Input Port register is read.  
Note that changing an I/O from and output to an input may cause a false interrupt to occur  
if the state of the pin does not match the contents of the Input Port register.  
6.4 I/O port  
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a  
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.  
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the  
state of the Output Port register. Care should be exercised if an external voltage is applied  
to an I/O configured as an output because of the low-impedance paths that exist between  
the pin and either VDD or VSS  
.
PCA9534  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2017. All rights reserved.  
Product data sheet  
Rev. 4 — 7 November 2017  
7 of 27  
 
 
 
 
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