PCA9504ADGG-T

更新时间： 2024-02-18 02:43:49

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
29页	146K
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PCA9504ADGG-T 数据手册

Philips Semiconductors

Product data

Glue chip 4

PCA9504A

PIN DESCRIPTION CONTINUED

PIN(S)

SYMBOL

FUNCTION

VSYNCH input from chipset video

VSYNC_3V

HSYNC_5V

VSYNC_5V

HSYNCH output to monitor

VSYNCH output to monitor

CCP

_VREF

Analog voltage reference for determining INIT/A20M input thresh-

olds

3IV/3O

STRAP

Strapping option for GP or FLUSH mode (internal pull-up resistor)

Note 1

GP3_IN

Generic logic gate 3 input

Generic logic gate 3 output

5V OD

GP3_OUT

NOTE:

1. The pin is internally pulled up to default to FLUSH mode.

TYPE DESCRIPTION

3.3 V input signal

3IU

3.3 V input signal with internal pull-up

5 V input signal

5IU

5ID

5 V input signal with internal pull-up

5 V input signal with internal pull-down

Power (input)

Ground (input)

3.3 V output signal

5 V output signal

3V OD

5V OD

3.3 V open-drain output signal

5 v open-drain output signal

Analog output

Analog input

3IOD

5IOD

REFL

3.3 V input/output open-drain

5 V input/output open-drain

Input voltage levels referenced to V

_VREF

CCP

FUNCTION TABLES

Strapping Selection Pin

STRAP (pin 54)

MODE

PIN NAME & (PIN NUMBER)

1 No connect

0 GND

FLUSH

GPO_FLUSH_CACHE (4)

A20M (5)

INIT (6)

FLUSH_OUT_CPU (7)

INIT_OUT (8)

GP2_IN (4)

0 GND

GP1_INB (5)

GP1_INA (6)

GP1_OUT (7)

GP2_OUT (8)

0 GND

NOTE:

1. The pin is internally pulled up to default to FLUSH mode.

2004 May 11

1 2 345 6 7...29

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