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PCA6107

更新时间： 2024-02-02 14:11:21

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
24页	307K
描述
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

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技术参数
数据手册

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PCA6107 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOIC-18	针数：	18
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.37
Is Samacsys：	N	JESD-30 代码：	R-PDSO-G18
长度：	11.55 mm	位数：	8
I/O 线路数量：	8	端口数量：	1
端子数量：	18	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP18,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	2.5/5 V	认证状态：	Not Qualified
座面最大高度：	2.65 mm	子类别：	Parallel IO Port
最大供电电压：	5.5 V	最小供电电压：	2.3 V
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	7.5 mm
uPs/uCs/外围集成电路类型：	PARALLEL IO PORT, GENERAL PURPOSE	Base Number Matches：	1

PCA6107 数据手册

PCA6107

REMOTE 8-BIT I²C AND SMBus LOW-POWER I/O EXPANDER

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

www.ti.com

SCPS139B–JANUARY 2006–REVISED OCTOBER 2006

Reads

The bus master first must send the PCA6107 address with the least-significant bit set to a logic 0 (see Figure 4

for device address). The command byte is sent after the address and determines which register is accessed.

After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data

from the register defined by the command byte then is sent by the PCA6107 (see Figure 8 and Figure 9). After a

restart, the value of the register defined by the command byte matches the register being accessed when the

restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no

limitation on the number of data bytes received in one read transmission, but when the final byte is received, the

bus master must not acknowledge the data.

ACK From

Master

ACK From

Slave

ACK From

Slave

ACK From

Slave

Data from Register

Slave Address

Command Byte

1 A2 A1 A0

Data

1 A2 A1 A0

First byte

R/W

At this moment, master-transmitter

becomes master-receiver, and

slave-receiver becomes

slave-transmitter

NACK From

Master

Data from Register

Data

Last Byte

Figure 8. Read From Register

<br/>

SCL

SDA

Data From Port

Data 1

Slave Address

Data From Port

Data 4

A2 A1 A0

R/W

Start

Condition

NACK From

ACK From

Slave

ACK From

Master

Stop

Condition

Master

Read From

Port

Data Into

Port

Data 2

Data 3

Data 4

Data 5

INT

A. This figure assumes the command byte has been programmed previously with 00h.

B. Transfer of data can be stopped at any moment by a Stop condition. When this occurs, data present at the last

acknowledge phase is valid (output mode). Input data is lost.

C. This figure eliminates the command byte transfer, a restart and slave address call between the initial slave address

call and actual data transfer from the P port (see Figure 8 for these details).

Figure 9. Read Input Port Register

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与PCA6107相关器件

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PCA6107DW	TI	REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIG	获取价格
PCA6107DWG4	TI	REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIG	获取价格
PCA6107DWR	TI	REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIG	获取价格
PCA6107DWRG4	TI	REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIG	获取价格
PCA6107DWT	TI	8 I/O, PIA-GENERAL PURPOSE, PDSO18, SOIC-18	获取价格
PCA-6108	ADVANTECH	ISA-bus Passive Backplane	获取价格

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