TM
ispPAC 80
In-System Programmable Analog Circuit
Features
Functional Block Diagram
• IN-SYSTEM PROGRAMMABLE (ISP™) ANALOG
— Instrument Amplifier Gain Stage
— Precision Active Filtering (50kHz to 500kHz)
— Continuous-Time Fifth Order Low Pass Topology
— Dual, A/B Configuration Memory
TMS
TCK
TDI
1
2
3
4
5
6
7
8
16 VS
15 TEST
14 OUT+
13 OUT–
12 TEST
11 IN+
— Non-Volatile E2CMOS Cells
IA
2
OA
— IEEE 1149.1 JTAG Serial Port Programming
5th Order LPF
2
• UNIQUE FLEXIBILITY AND PERFORMANCE
— Programmable Gain Range (0dB to 20dB)
— Implements Multiple Filter Types: Elliptical,
Chebyshev, Bessel, Butterworth, Linear Phase,
Gaussian and Legendre
TDO
CS
E CMOS Cfg A
E CMOS Cfg B
CAL
Ref & Auto-Cal
ISP Control
— Low Distortion (THD < -74dB max @ 100kHz)
— Auto-Calibrated Input Offset Voltage
ENSPI
GND
10 IN–
9
VREFOUT
• TRUE DIFFERENTIAL I/O
— High CMR (58dB) Instrument Amplifier Input
— 2.5V Common Mode Reference on Chip
— Rail-to-Rail Voltage Outputs
ispPAC80
• SINGLE SUPPLY 5V OPERATION
— Power Dissipation of 165mW
Description
— 16-Pin Plastic SOIC, PDIP Packages
The ispPAC80 is a member of the Lattice family of In-System
Programmable analog circuits, digitally configured via non-
volatile E2CMOS® technology.
• APPLICATIONS INCLUDE INTEGRATED
— Single +5V Supply Signal Conditioning
— Programmable Filters With Fully Differential I/O
— Analog Front Ends, 12-Bit Data Acq. Systems
— DSP System Front End Signal Conditioning
— High-Performance Reconstruction Filters
Analog building blocks, called PACell™(s), replace traditional
analog components such as opamps, eliminating the need for
external resistors and capacitors. With no requirement for
external configuration components, ispPAC80 expedites the
design process, simplifying prototype circuit implementation
andchange, whileprovidinghigh-performanceintegratedfunc-
tionality. With all components on chip, there is no longer a
concern of performance degradation due to component mis-
matchorotherexternalfactors.TheispPAC80providesreliable
and repeatable performance, every time.
Typical Application Diagram
5V
5V
12-Bit Differential
Input ADC
ispPAC80
Designers configure the ispPAC80 and verify its performance
using PAC-Designer™, an easy to use, Microsoft Windows®
compatibleprogram. Afilterconfigurationdatabaseisprovided
whereby thousands of different configurations can be realized.
No special understanding of filter synthesis is required beyond
that of general specifications such as corner frequency and
stopband attenuation, etc. The software lists the possible
choices that meet the designer’s specifications which can then
be loaded directly into either of two device
(A/B) configurations from the lookup table. Device program-
ming is supported using PC parallel port I/O operations.
Ain+
Ain-
Vin
A/B & Gain
SPI Control
VREFout
5V
Reference
DSP
The ispPAC80 is configured through its IEEE Standard 1149.1
compliant serial port. The flexible In-System Programming
capability enables programming, verification and reconfig-
uration, if desired, directly on the printed circuit board.
Copyright©2000LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-888-477-7537; FAX (503) 268-8037; http://www.latticesemi.com
March 2000
pac80_03
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