80C32/80C52
CMOS 0 to 44 MHz Single Chip 8–bit Microcontroller
1. Description
TEMIC’s 80C52 and 80C32 are high performance
CMOS versions of the 8052/8032 NMOS single chip 8
bit Microcontroller.
software-selectable modes of reduced activity for
further reduction in power consumption. In the idle
mode the CPU is frozen while the RAM, the timers, the
serial port and the interrupt system continue to function.
In the power down mode the RAM is saved and all other
functions are inoperative.
The fully static design of the TEMIC 80C52/80C32
allows to reduce system power consumption by bringing
the clock frequency down to any value, even DC,
without loss of data.
The 80C32 is identical to the 80C52 except that it has no
on-chip
ROM.
TEMIC’s
80C52/80C32
are
The 80C52 retains all the features of the 8052: 8 K bytes
of ROM; 256 bytes of RAM; 32 I/O lines; three 16 bit
timers; a 6-source, 2-level interrupt structure; a full
duplex serial port; and on-chip oscillator and clock
manufactured using SCMOS process which allows them
to run from 0 up to 44 MHz with VCC = 5 V.
TEMIC’s 80C52 and 80C32 are also available at
16 MHz with 2.7 V < VCC < 5.5 V.
circuits.
In
addition,
the
80C52
has
2
D 80C32: Romless version of the 80C52
D 80C32/80C52-L16: Low power version
D 80C32-40: 0 to 40 MHz(1)
D 80C32-42: 0 to 42 MHz(1)
D 80C32-44: 0 to 44 MHz(1)
VCC: 2.7 – 5.5 V
Freq: 0-16 MHz
D 80C32/80C52-12: 0 to 12 MHz
D 80C32/80C52-16: 0 to 16 MHz
D 80C32/80C52-20: 0 to 20 MHz
D 80C32/80C52-25: 0 to 25 MHz
D 80C32/80C52-30: 0 to 30 MHz
D 80C32/80C52-36: 0 to 36 MHz
Notes:
1. 0 to 70_C temperature range.
2. For other speed and temperature range availability, please
contact your sales office.
2. Features
D Power control modes
D Fully static design
D 256 bytes of RAM
D 0.8µ CMOS process
D 8 Kbytes of ROM (80C52)
D 32 programmable I/O lines
D Three 16 bit timer/counters
D 64 K program memory space
D 64 K data memory space
D Boolean processor
D 6 interrupt sources
D Programmable serial port
D Temperature range: commercial, industrial, automotive,
military
3. Optional
D Secret ROM: Encryption
D Secret TAG: Identification number
1
Rev. I – September 18, 1998