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P52123DC PDF预览

P52123DC

更新时间: 2024-09-30 09:56:03
品牌 Logo 应用领域
PLL 石英晶振压控振荡器
页数 文件大小 规格书
6页 211K
描述
Low Phase Noise PECL VCXO (100MHz to 200MHz)

P52123DC 数据手册

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P521-23  
Low Phase Noise PECL VCXO (100MHz to 200MHz)  
PAD ASSIGNMENT AND DESCRIPTION  
Pin #  
Name  
Description  
Oscillator Off Selection input pad. When low, turns off the oscillator when output is disabled.  
When high (default), oscillator running when output is disabled.  
1
OSCOFFSEL  
Internal pull-up  
2
3
GNDOSC  
VCON  
GND connection for oscillator circuitry.  
Control Voltage input. Use this pin to change the output frequency by varying the applied  
Control Voltage.  
4
5
XIN  
XOUT  
OECTRL  
DNC  
Crystal oscillator input pin.  
Crystal oscillator output pin.  
OE input pad. See table on page 1.  
Do Not Connect.  
6
7
8
GND  
Ground connection.  
9
GND  
Ground connection.  
10  
11  
Q
PECL Output.  
QBAR  
PECL complementary output.  
VDD connection for output buffer circuitry.  
VDDBUF should be separately decoupled from other VDDs whenever possible.  
VDD connection for analog circuitry.  
12  
13  
VDDBUF  
VDDANA  
VDDANA should be separately decoupled from other VDDs whenever possible.  
14  
15  
OESEL  
Selector input to choose the OE control logic. See table on page 1.  
BUFZSEL  
Output impedance selector  
VDD connection for oscillator circuitry.  
VDDOSC should be separately decoupled from other VDDs whenever possible.  
16  
VDDOSC  
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 [www.phaselink.com]  
Rev 7/28/04 Page 2  

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