Datasheet > P521-29

P521-29

更新时间： 2024-09-30 09:56:03

品牌	Logo	应用领域
PLL		振荡器石英晶振压控振荡器
页数	文件大小	规格书
6页	104K
描述
Low Phase Noise LVDS VCXO (100MHz to 200MHz)

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中文翻译

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数据手册

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P521-29 数据手册

Preliminary P521-29

Low Phase Noise LVDS VCXO (100MHz to 200MHz)

FEATURES

DIE CONFIGURATION

57.5 mil

100MHz to 200MHz Fundamental Mode Crystal.

Output range: 100MHz – 200MHz.

Complementary LVDS outputs.

Selectable OE Logic (enable high or enable low).

Integrated variable capacitors.

High pull linearity: < 5%.

+/- 125 ppm pull range

Supports 2.5V or 3.3V-Power Supply.

Available in die form.

(1460,1435)

GNDOSC

VCON

XIN

VDDANA

VDDBUF

PECLBAR

PECL

XOUT

GNDBUF

Thickness 10 mil.

(0,0)

DESCRIPTIONS

P521-29 is a VCXO IC specifically designed to pull

high frequency fundamental crystals. Its internal

varicaps allow an on chip frequency pulling,

controlled by the VCON input. The chip provides a

low phase noise, low jitter LVDS differential clock

output.

DIE SPECIFICATIONS

Name

Value

Size

56.5 x 57.5 mil

GND

Reverse side

Pad dimensions

Thickness

80 micron x 80 micron

10 mil

BLOCK DIAGRAM

OUTPUT ENABLE LOGIC SELECTION

Oscillator

VCON

Amplifier

OESEL

(Pad #14)

OECTRL

(Pad #22)

State

X+

integrated

Tri-state

varicaps

0 (Default)

X-

1 (Default)

0 (Default)

Output enabled

Tri-state

P521-29

Pad #14, 22: Bond to GND to set to “0”, bond to VDD to set to “1”

No connection results to “default” setting through internal pull-up/-down.

Pad #22: Logical states defined by CMOS V_IHand V_ILlevels.

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 3/02/04 Page 1

12 3 4 5 6

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