Datasheet > P01N02LJA

P01N02LJA

更新时间： 2022-12-22 00:20:29

品牌	Logo	应用领域
其他 - ETC		晶体晶体管场效应晶体管
页数	文件大小	规格书
3页	110K
描述
N-Channel Logic Level Enhancement Mode Field Effect Transistor(Preliminary)

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P01N02LJA 数据手册

N-Channel Logic Level Enhancement Mode

Field Effect Transistor

NIKO-SEM

P01N02LJA

J-LEAD8

( Preliminary)

DYNAMIC

Input Capacitance

C_iss

120

_GS= 0V, V_DS= 15V, f = 1MHz

Output Capacitance

Reverse Transfer Capacitance

Total Gate Charge²

Gate-Source Charge²

Gate-Drain Charge²

Turn-On Delay Time²

Rise Time²

C_oss

C_rss

Q_g

100

3.0

5.8

V_DS= 0.5V_(BR)DSS, V_GS= 10V,

I_D= 1A

Q_gs

Q_gd

t_d(on)

t_r

V_DS= 15V, R_L= 1Ω

Turn-Off Delay Time²

t_d(off)

I_D≅ 1A, V_GS= 10V, R_GS= 50Ω

Fall Time²

t_f

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (T_C= 25 °C)

Continuous Current

I_S

I_SM

V_SD

t_rr

1.2

Pulsed Current³

Forward Voltage¹

I_F= I_S, V_GS= 0V

1.3

Reverse Recovery Time

Reverse Recovery Charge

µC

I_F= I_S, dl_F/dt = 100A / µS

Q_rr

0.22

¹Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％.

²Independent of operating temperature.

³Pulse width limited by maximum junction temperature.

REMARK: THE PRODUCT MARKED WITH “102B”

AUG-30-2002

123

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