OXCB950
OXFORD SEMICONDUCTOR LTD.
7.6.4
7.7
SLEEP MODE............................................................................................................................................................... 40
MODEM INTERFACE ....................................................................................................................................................... 40
MODEM CONTROL REGISTER ‘MCR’........................................................................................................................ 40
MODEM STATUS REGISTER ‘MSR’ ........................................................................................................................... 41
OTHER STANDARD REGISTERS ................................................................................................................................... 41
DIVISOR LATCH REGISTERS ‘DLL & DLM’................................................................................................................ 41
SCRATCH PAD REGISTER ‘SPR’ ............................................................................................................................... 41
AUTOMATIC FLOW CONTROL....................................................................................................................................... 42
ENHANCED FEATURES REGISTER ‘EFR’................................................................................................................. 42
SPECIAL CHARACTER DETECTION.......................................................................................................................... 43
AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................... 43
AUTOMATIC OUT-OF-BAND FLOW CONTROL ......................................................................................................... 43
7.7.1
7.7.2
7.8
7.8.1
7.8.2
7.9
7.9.1
7.9.2
7.9.3
7.9.4
7.10 BAUD RATE GENERATION............................................................................................................................................. 44
7.10.1
7.10.2
7.10.3
7.10.4
7.10.5
GENERAL OPERATION............................................................................................................................................... 44
CLOCK PRESCALER REGISTER ‘CPR’...................................................................................................................... 44
TIMES CLOCK REGISTER ‘TCR’................................................................................................................................. 44
EXTERNAL 1X CLOCK MODE..................................................................................................................................... 46
CRYSTAL OSCILLATOR CIRCUIT .............................................................................................................................. 46
7.11 ADDITIONAL FEATURES ................................................................................................................................................ 46
7.11.1
7.11.2
7.11.3
7.11.4
7.11.5
7.11.6
7.11.7
7.11.8
7.11.9
ADDITIONAL STATUS REGISTER ‘ASR’ .................................................................................................................... 46
FIFO FILL LEVELS ‘TFL & RFL’ ................................................................................................................................... 47
ADDITIONAL CONTROL REGISTER ‘ACR’................................................................................................................. 47
TRANSMITTER TRIGGER LEVEL ‘TTL’ ...................................................................................................................... 48
RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ...................................................................................................... 48
FLOW CONTROL LEVELS ‘FCL’ & ‘FCH’.................................................................................................................... 48
DEVICE IDENTIFICATION REGISTERS...................................................................................................................... 49
CLOCK SELECT REGISTER ‘CKS’.............................................................................................................................. 49
NINE-BIT MODE REGISTER ‘NMR’............................................................................................................................. 49
7.11.10 MODEM DISABLE MASK ‘MDM’.................................................................................................................................. 50
7.11.11 READABLE FCR ‘RFC’................................................................................................................................................. 50
7.11.12 GOOD-DATA STATUS REGISTER ‘GDS’.................................................................................................................... 51
7.11.13 DMA STATUS REGISTER ‘DMS’ ................................................................................................................................. 51
7.11.14 PORT INDEX REGISTER ‘PIX’..................................................................................................................................... 51
7.11.15 CLOCK ALTERATION REGISTER ‘CKA’..................................................................................................................... 51
8
SERIAL EEPROM SPECIFICATION ..................................................................................................... 52
EEPROM DATA ORGANISATION ................................................................................................................................... 52
ZONE0: HEADER ......................................................................................................................................................... 52
ZONE1 : POWER MANAGEMENT DATA AND DATA_SCALE ZONE ...................................................................... 53
ZONE2: LOCAL CONFIGURATION REGISTER ZONE............................................................................................... 53
ZONE 3 : CARDBUS INFORMATION STRUCTURE ................................................................................................... 53
ZONE4: PCI CONFIGURATION REGISTERS ............................................................................................................. 54
ZONE5: FUNCTION ACCESS...................................................................................................................................... 54
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
9
10
11
COMPLIANCE TO PC CARD STANDARDS, 7.0 AND 7.1 .................................................................. 56
OPERATING CONDITIONS ............................................................................................................... 59
DC ELECTRICAL CHARACTERISTICS............................................................................................ 60
11.1 NORMAL 3.3V I/O BUFFERS........................................................................................................................................... 60
11.2 5.0V TOLERANT I/O BUFFERS...................................................................................................................................... 60
12
AC ELECTRICAL CHARACTERISTICS............................................................................................ 61
12.1 DUAL MODE (CARDBUS/PCI) I/O BUFFERS................................................................................................................ 61
13
POWER CONSUMPTION MEASUREMENTS................................................................................... 62
13.1 STATIC CURRENT CONSUMPTION ............................................................................................................................... 62
13.2 CURRENT CONSUMPTION IN APPLICATION ............................................................................................................... 62
DS-0033 Sep 05
External-Free Release
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