INTRODUCTION
Target Readers
This manual is intended for users who wish to understand the functions of the
memory controllers (NT85E500, NDT85E500V10, NT85E502) for the NU85EA,
NU85ET, and NDU85ETV14 CPU cores for CBICs and who design application
systems using these CPU cores.
Memory Controller
Target CPU Core
NU85EA, NU85ET
NDU85ETV14
NT85E500, NT85E502 (CB-10 Family VX Type)
NDT85E500V10 (CB-12 Family L Type)
Purpose
This manual’s purpose is to help the user understand the functions of the NT85E500,
NDT85E500V10, and NT85E502.
Organization
This manual consists of the following.
CHAPTER 1 NT85E500
This chapter explains the NT85E500, which is the basic macro for controlling
external memory.
The NT85E500 is a memory controller for the NU85EA, NU85ET, and
NDU85ETV14. The NT85E500 and NDT85E500V10 contain an on-chip SRAM,
I/O controller, and page ROM controller.
CHAPTER 2 NT85E502
This chapter explains the NT85E502, which is an SDRAM controller.
How to Use This Manual
This manual assumes that the reader has general knowledge of electrical
engineering, logic circuits, microcontrollers, SRAM, page ROM, and SDRAM.
To gain a general understanding of the NT85E500, NDT85E500V10, and NT85E502
functions:
→ Read this manual according to the CONTENTS.
To confirm details of a function, etc. when the name is known
→ Refer to APPENDIX B INDEX.
To know the functions of the NU85EA in detail:
→ Refer to NU85E Hardware User’s Manual (A14874E).
To know the functions of the NU85ET and NDU85ETV14 in detail:
→ Refer to NU85ET Hardware User’s Manual (A15015E).
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Preliminary User's Manual A15019EJ3V0UM