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NT5CB128M16FP-EJ PDF预览

NT5CB128M16FP-EJ

更新时间: 2024-01-18 08:10:56
品牌 Logo 应用领域
南亚科技 - NANYA 动态存储器双倍数据速率
页数 文件大小 规格书
163页 6978K
描述
Commercial, Industrial and Automotive DDR3(L) 2Gb SDRAM

NT5CB128M16FP-EJ 数据手册

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Nanya Technology Corp.  
NT5CB(C)256M8FN / NT5CB(C)128M16FP  
Commercial, Industrial and Automotive DDR3(L) 2Gb SDRAM  
Features  
Signal Integrity  
JEDEC DDR3 Compliant  
- Configurable DS for system compatibility  
- Configurable On-Die Termination  
- 8n Prefetch Architecture  
- Differential Clock(CK/) and Data Strobe(DQS/)  
- Double-data rate on DQs, DQS and DM  
Data Integrity  
- ZQ Calibration for DS/ODT impedance accuracy via  
external ZQ pad (240 ohm ± 1%)  
Signal Synchronization  
- Write Leveling via MR settings 7  
- Auto Self Refresh (ASR) by DRAM built-in TS  
- Auto Refresh and Self Refresh Modes  
Power Saving Mode  
- Read Leveling via MPR  
Interface and Power Supply  
- Partial Array Self Refresh (PASR)1  
- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)  
- SSTL_1354 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)  
- Power Down Mode  
Options  
Speed Grade (CL-TRCD-TRP) 2,3  
Temperature Range (Tc) 5  
- Commercial Grade = 0~95℃  
- 2133 Mbps / 14-14-14  
- Industrial Grade (-I) = -40~95℃  
- Automotive Grade 2 (-H) = -40~105℃  
- Automotive Grade 3 (-A) = -40~95℃  
- 1866 Mbps / 12-12-12,13-13-13  
- 1600 Mbps / 11-11-11  
Programmable Functions  
Self RefreshTemperature Range(Normal/Extended)  
Output Driver Impedance (34/40)  
CAS Latency (5/6/7/8/9/10/11/12/13/14)  
CAS Write Latency (5/6/7/8/9/10)  
On-Die Termination of Rtt_Nom(20/30/40/60/120)  
On-Die Termination of Rtt_WR(60/120)  
Precharge Power Down (slow/fast)  
Additive Latency (0/CL-1/CL-2)  
Write Recovery Time (5/6/7/8/10/12/14/16)  
Burst Type (Sequential/Interleaved)  
Burst Length (BL8/BC4/BC4 or 8 on the fly)  
Packages / Density Information  
Density and Addressing  
256Mb x 8  
Lead-free RoHS compliance and Halogen-free  
Organization  
128Mb x 16  
2Gb  
Length x Width  
(mm)  
Ball pitch  
(mm)  
Bank Address  
Auto precharge  
BL switch on the fly  
Row Address  
Column Address  
Page Size  
BA0 BA2  
A10 / AP  
A12 /   
A0 A14  
A0 A9  
1KB  
BA0 BA2  
A10 / AP  
A12 /   
A0 A13  
A0 A9  
2KB  
(Org. / Package)  
78-ball  
256Mbx8  
8.00 x 10.50  
9.00 x 13.00  
0.80  
0.80  
TFBGA  
96-ball  
tREFI(us) 5  
tRFC(ns) 6  
Tc<=85:7.8, Tc>85:3.9  
160ns  
128Mbx16  
TFBGA  
NOTE 1 Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand.  
NOTE 2 The timing specification of high speed bin is backward compatible with low speed bin.  
NOTE 3 Please refer to ordering information for the deailts (DDR3, DDR3L, DDR3L RS).  
NOTE 4 SSTL_135 compatible to SSTL_15. That means 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. 1.35V DDR3L-RS parts are exceptional  
and unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts.  
NOTE 5 If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended SRT or ASR must be enabled.  
NOTE 6 Violating tRFC specification will induce malfunction.  
NOTE 7 Only Support prime DQs feedback for each byte lane.  
Version 1.7  
04/2015  
1
Nanya Technology Cooperation ©  
NTC has the rights to change any specifications or product without notification.  
All Rights Reserved.  

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