Datasheet > NT3883H

NT3883H

更新时间： 2024-02-05 06:11:15

品牌	Logo	应用领域
其他 - ETC		驱动器
页数	文件大小	规格书
12页	291K
描述
Dot Matrix LCD 80-Channel Driver

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数据手册

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NT3883H 技术参数

生命周期：	Contact Manufacturer	包装说明：	QFP, QFP100,.7X.9,32
Reach Compliance Code：	unknown	风险等级：	5.76
Is Samacsys：	N	显示模式：	SEGMENT
JESD-30 代码：	R-PQFP-G100	区段数：	80
端子数量：	100	最高工作温度：	70 °C
最低工作温度：	-20 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP100,.7X.9,32
封装形状：	RECTANGULAR	封装形式：	FLATPACK
电源：	5 V	认证状态：	Not Qualified
子类别：	Other Interface ICs	最大压摆率：	0.5 mA
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	Base Number Matches：	1

NT3883H 数据手册

NT3883

Functional Description

NT3883 is a dot matrix LCD segment driver LSI. It

operates with the controller, such as NT3881B/C/D,

and/or another segment driver LSI NT3882A/3883.

NT3883 receives serial data from the controller or

another NT3883, converts it to parallel data and then

supplies the LCD driving waveforms to the LCD panel.

5. DL2

Data input/output of the 41^st- 80^thregister. When SL2 is

connected to GND, the data from LCD controller is fed

into the 41^st- 80^thregister through DL2 serially. If SL2 is

connected to V_DD, the DL2 becomes the output of the

41^st- 80^thregister.

1. CL1

6. DR2

This signal is used for latching the shift register contents.

When CL1 is set at high, the shift register contents are

transferred to the 80-bit 4level LCD driver. When CL1 is

set at low, the last display output data (S1 to S80) is

held.

Data input/output of the 41^st- 80^thregister. When SL2 is

connected to GND, the 80^thbit of the 41^st- 80^thregister

output from DR2. By connecting DR2 to DL1 of next

NT3882A/3883, the cascade structure is obtained to

drive a wider LCD panel. If SL2 is connected to V_DD, the

DR2 becomes the input of the 41^st- 80^thregister, in this

case, the data may come from the next NT3882A/3883.

2. CL2

Clock pulse inputs for the two 40-bit shift registers. The

data is shifted to an 80-bit latch at the falling edge of

CL2. The clock signal CL2 must be active when

operating to refresh shift registers' contents.

7. SL1

The shift direction of S1 to S40, i.e. 1^stto 40^thshift

description is listed in Note*4 of Page5.

3. DL1

Data input/output of the 1^st- 40^thregister. When SL1 is

connected to GND or open, the data from LCD controller

is fed into the 1^st- 40^thregister through DL1 serially. If

SL1 is connected to V_DD, the DL1 becomes the output of

the 1^st- 40^thregister.

8. SL2

The shift direction of S41 to S80, i.e. 41^stto 80^thshift

description is listed in Note*4 of Page5.

9. S1 to S80

4. DR1

LCD driver output pins. These 80 bits represent the 80

Data input/output of the 1^st- 40^thregister. When SL1 is

connected to GND, the 20^thbit of the 1^st- 40^thregister

output from DR1. By connecting DR1 to DL2, two 40-bit

shift registers cascaded to one 80-bit shift register. If

SL1 is connected to V_DD, the DR1 becomes the input of

the 1^st- 40^thregister, in this case, the data may come

from DL2.

data bits in the 80-bit latch and one of V , V , V and

is selected as a LCD driving voltage source

according to the combination of latched data level and

the alternate signal (M). The truth table is listed as

follows:

Latched Data

1(High)

Output Level of S1 to S80

1(High)

0(Low)

1(High)

0(Low)

V_EE

V_DD

V₃

(Selected)

0(Low)

(Non-selected)

V₂

1...4 5 678 9 10...12

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