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NM27C010T90 PDF预览

NM27C010T90

更新时间: 2024-10-02 20:24:47
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飞兆/仙童 - FAIRCHILD /
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10页 118K
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NM27C010T90 数据手册

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October 1998  
NM27C010  
1,048,576-Bit (128K x 8) High Performance  
CMOS EPROM  
The NM27C010 is manufactured using Fairchild’s advanced  
CMOS AMG™ EPROM technology.  
General Description  
The NM27C010 is a high performance, 1,048,576-bit Electrically  
Programmable UV Erasable Read Only Memory. It is organized  
as 128K-words of 8 bits each. Its pin-compatibility with byte-wide  
JEDEC EPROMs enables upgrades through 8 Mbit EPROMs.  
The “Don’t Care” feature during read operations allows memory  
expansions from 1M to 8M bits with no printed circuit board  
changes.  
The NM27C010 is one member of a high density EPROM Family  
which range in densities up to 4 Megabit.  
Features  
High performance CMOS  
70 ns access time  
TheNM27C010candirectlyreplacelowerdensity28-pinEPROMs  
by adding an A16 address line and VCC jumper. During the normal  
read operation PGM and VPP are in a “Don’t Care” state which  
allows higher order addresses, such as A17, A18, and A19 to be  
connected without affecting the normal read operation. This  
allows memory upgrades to 8M bits without hardware changes.  
The NM27C010 is also offered in a 32-pin plastic DIP with the  
same upgrade path.  
Fast turn-off for microprocessor compatibility  
Simplified upgrade path  
VPP and PGM are “Don’t Care” during normal read  
operation  
Manufacturers identification code  
Fast programming  
JEDEC standard pin configurations  
32-pin PDIP package  
32-pin PLCC package  
The NM27C010 provides microprocessor-based systems exten-  
sive storage capacity for large portions of operating system and  
application software. Its 70 ns access time provides no-wait-state  
operation with high-performance CPUs. The NM27C010 offers a  
single chip solution for the code storage requirements of 100%  
firmware-based equipment. Frequently-used software routines  
are quickly executed from EPROM storage, greatly enhancing  
system utility.  
32-pin CERDIP package  
Block Diagram  
Data Outputs O - O  
0
7
V
CC  
GND  
V
PP  
OE  
CE  
Output Enable,  
Chip Enable, and  
Program Logic  
Output  
Buffers  
PGM  
Y Decoder  
1,048,576-Bit  
Cell Matrix  
A
- A  
16  
0
Address  
Inputs  
X Decoder  
DS010798-1  
© 1998 Fairchild Semiconductor Corporation  
1
www.fairchildsemi.com  
NM27C010 ver. 1.1  

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