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NLU1GT50 PDF预览

NLU1GT50

更新时间: 2024-02-08 22:05:08
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 95K
描述
Single Buffer, Non-Inverting, TTL Level

NLU1GT50 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:DFN包装说明:VSON, SOLCC6,.04,16
针数:6Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:1.3
系列:1GJESD-30 代码:R-PDSO-N6
JESD-609代码:e4长度:1.2 mm
负载电容(CL):50 pF逻辑集成电路类型:BUFFER
最大I(ol):0.004 A湿度敏感等级:1
功能数量:1输入次数:1
端子数量:6最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:VSON封装等效代码:SOLCC6,.04,16
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:1.8/5 VProp。Delay @ Nom-Sup:22 ns
传播延迟(tpd):25.5 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:0.55 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.4 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:1 mmBase Number Matches:1

NLU1GT50 数据手册

 浏览型号NLU1GT50的Datasheet PDF文件第2页浏览型号NLU1GT50的Datasheet PDF文件第3页浏览型号NLU1GT50的Datasheet PDF文件第4页浏览型号NLU1GT50的Datasheet PDF文件第5页浏览型号NLU1GT50的Datasheet PDF文件第6页浏览型号NLU1GT50的Datasheet PDF文件第7页 
NLU1GT50  
Single Buffer,  
Non-Inverting, TTL Level  
TTL-Compatible Inputs  
The NLU1GT50 MiniGatet is an advanced CMOS high-speed  
non-inverting buffer in ultra-small footprint.  
http://onsemi.com  
MARKING  
DIAGRAMS  
The device input is compatible with TTL-type input thresholds and  
the output has a full 5.0 V CMOS level output swing.  
The NLU1GT50 input and output structures provide protection  
when voltages up to 7.0 V are applied, regardless of the supply  
voltage.  
UDFN6  
MU SUFFIX  
CASE 517AA  
LM  
1
1
Features  
ꢀDesigned for 1.65 to 5.5 V V Operation  
CC  
ULLGA6  
1.0 x 1.0  
CASE 613AD  
LM  
LM  
LM  
ꢀHigh Speed: t = 3.5 ns (Typ) @ V = 5.0 V  
PD  
CC  
ꢀLow Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
ꢀTTL-Compatible Input: V = 0.8 V; V = 2.0 V, V = 5.0 V  
IL  
IH  
CC  
ꢀCMOS-Compatible Output:  
OH  
ULLGA6  
1.2 x 1.0  
CASE 613AE  
V
> 0.8 V ; V < 0.1 V @ Load  
CC OL CC  
ꢀPower Down Protection Provided on inputs  
ꢀBalanced Propagation Delays  
ꢀUltra-Small Packages  
1
ULLGA6  
1.45 x 1.0  
CASE 613AF  
ꢀThese are Pb-Free Devices  
1
NC  
IN A  
GND  
1
2
3
6
5
V
CC  
L
= Device Marking  
= Date Code  
M
NC  
PIN ASSIGNMENT  
1
2
3
4
5
6
NC  
IN A  
4
OUT Y  
GND  
OUT Y  
NC  
Figure 1. Pinout (Top View)  
V
CC  
1
IN A  
OUT Y  
FUNCTION TABLE  
A
Y
Figure 2. Logic Symbol  
L
L
H
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
©ꢀ Semiconductor Components Industries, LLC, 2008  
March, 2008 - Rev. 2  
1
Publication Order Number:  
NLU1GT50/D  

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