Datasheet > N04Q1625C2BB2-70I

N04Q1625C2BB2-70I

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
NANOAMP		静态存储器
页数	文件大小	规格书
13页	300K
描述
4Mb Ultra-Low Power Asynchronous CMOS SRAM w/ Dual Vcc and VccQ for Ultimate Power Reduction 256K】16 bit POWER SAVER TECHNOLOGY

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N04Q16yyC2B

NanoAmp Solutions, Inc.

Timing Test Conditions

Advance Information

Item

0.1V_CCto 0.9 V_CC

Input Pulse Level

Input Rise and Fall Time

Input and Output Timing Reference Levels

Output Load

5ns

0.5 V_CC

CL = 30pF

0 to +70^oC

Operating Temperature

Timing

-70

-150

Units

Item

Symbol

Min.

Max.

Min.

Max.

t_RC

t_AA

Read Cycle Time

150

Address Access Time

150

t_AAP

t_CO

t_OE

Page Mode Address Access Time

Chip Enable to Valid Output

150

Output Enable to Valid Output

Byte Select to Valid Output

t_{LB, UB}

150

t_LZ

Chip Enable to Low-Z output

Output Enable to Low-Z Output

Byte Select to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

Byte Select Disable to High-Z Output

Output Hold from Address Change

t_OLZ

t_{LBZ, UBZ}

t_HZ

t_OHZ

_LBHZ,t_UBHZ

t_OH

t_WC

t_CW

t_AW

Write Cycle Time

Chip Enable to End of Write

Address Valid to End of Write

Byte Select to End of Write

Write Pulse Width

150

120

100

t_{LBW, UBW}

t_WP

t_AS

Address Setup Time

t_WR

t_WHZ

t_DW

t_DH

Write Recovery Time

Write to High-Z Output

Data to Write Time Overlap

Data Hold from Write Time

End Write to Low-Z Output

100

t_OW

Stock No. 23451-B 2/06

The specification is ADVANCE INFORMATION and subject to change without notice.

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