Datasheet > N01M083WL1AN-70I

N01M083WL1AN-70I

更新时间： 2024-01-30 07:06:32

品牌	Logo	应用领域
NANOAMP		静态存储器
页数	文件大小	规格书
9页	224K
描述
SRAM

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技术参数
数据手册

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N01M083WL1AN-70I 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.8
Base Number Matches：	1

N01M083WL1AN-70I 数据手册

NanoAmp Solutions, Inc.

Functional Block Diagram

N01M083WL1A

Word

Address

Inputs

Address

Decode

Logic

A - A

Input/

Output

Mux

Page

16K Page

x 16 word

x 8 bit

Address

Inputs

Address

A - A

Decode

Logic

and

I/O - I/O

RAM Array

Buffers

CE1

CE2

Control

Logic

Functional Description

I/O₀- I/O₇

CE1

CE2

MODE

POWER

Standby¹

Write²

X²

High Z

Standby

Active

Data In

Data Out

High Z

Active

Read

Active

1. When the device is in standby mode, control inputs (WE and OE), address inputs and data input/outputs are internally isolated

from any external influence and disabled from exerting any influence externally.

2. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.

Capacitance

Item

Symbol

C_IN

Test Condition

Min

Max

Unit

V_IN= 0V, f = 1 MHz, T_A= 25^oC

Input Capacitance

I/O Capacitance

C_I/O

1. These parameters are verified in device characterization and are not 100% tested

Stock No. 23206-01 11/01/02

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

123 4 5 6 7...9

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