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N01L083WC2AT2-70I PDF预览

N01L083WC2AT2-70I

更新时间: 2024-02-03 01:12:28
品牌 Logo 应用领域
安森美 - ONSEMI 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
10页 162K
描述
Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, GREEN, TSOP1-32

N01L083WC2AT2-70I 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
包装说明:TSSOP, TSSOP32,.8,20Reach Compliance Code:unknown
风险等级:5.8最长访问时间:70 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G32
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP32,.8,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:PARALLEL电源:2.5/3.3 V
认证状态:Not Qualified最大待机电流:0.00001 A
最小待机电流:1.8 V子类别:SRAMs
最大压摆率:0.014 mA表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUALBase Number Matches:1

N01L083WC2AT2-70I 数据手册

 浏览型号N01L083WC2AT2-70I的Datasheet PDF文件第2页浏览型号N01L083WC2AT2-70I的Datasheet PDF文件第3页浏览型号N01L083WC2AT2-70I的Datasheet PDF文件第4页浏览型号N01L083WC2AT2-70I的Datasheet PDF文件第6页浏览型号N01L083WC2AT2-70I的Datasheet PDF文件第7页浏览型号N01L083WC2AT2-70I的Datasheet PDF文件第8页 
AMI Semiconductor, Inc.  
Timing Test Conditions  
N01L083WC2A  
Item  
0.1VCC to 0.9 VCC  
Input Pulse Level  
Input Rise and Fall Time  
Input and Output Timing Reference Levels  
Output Load  
5ns  
0.5 VCC  
CL = 30pF  
-40 to +85 oC  
Operating Temperature  
Timing  
2.3 - 3.6 V  
2.7 - 3.6 V  
Item  
Symbol  
Units  
Min.  
Max.  
Min.  
Max.  
tRC  
tAA  
Read Cycle Time  
70  
55  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
70  
70  
35  
55  
55  
30  
tCO  
tOE  
tLZ  
Chip Enable to Valid Output  
Output Enable to Valid Output  
Chip Enable to Low-Z output  
Output Enable to Low-Z Output  
Chip Disable to High-Z Output  
Output Disable to High-Z Output  
Output Hold from Address Change  
Write Cycle Time  
10  
5
10  
5
tOLZ  
tHZ  
0
20  
20  
0
15  
15  
tOHZ  
tOH  
tWC  
tCW  
tAW  
tWP  
tAS  
0
0
10  
70  
50  
50  
40  
0
10  
55  
45  
45  
32.5  
0
Chip Enable to End of Write  
Address Valid to End of Write  
Write Pulse Width  
Address Setup Time  
tWR  
tWHZ  
tDW  
tDH  
tOW  
Write Recovery Time  
0
0
Write to High-Z Output  
20  
15  
Data to Write Time Overlap  
Data Hold from Write Time  
End Write to Low-Z Output  
40  
0
30  
0
5
5
ns  
(DOC# 14-02-008 REV I ECN# 01-1283)  
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.  
5

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