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MX25L12873G PDF预览

MX25L12873G

更新时间: 2024-04-09 18:59:30
品牌 Logo 应用领域
旺宏电子 - Macronix /
页数 文件大小 规格书
111页 1504K
描述
Permanent 4 I/O, DTR, QPI, Individual Protection, H/W Reset

MX25L12873G 数据手册

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MX25L12873G  
2. GENERAL DESCRIPTION  
MX25L12873G is 128Mb bits Serial Flash memory, which is configured as 16,777,216 x 8 internally. When it is in  
two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. MX25L12873G feature a  
serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O  
mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial  
access to the device is enabled by CS# input.  
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits  
input and data output. When it is in four I/O read mode, the SI pin and SO pin become SIO0 pin, SIO1 pin, SIO2 pin  
and SIO3 pin for address/dummy bits input and data output.  
The MX25L12873G MXSMIO® (Serial Multi I/O) provides sequential read operation on the whole chip.  
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the  
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256  
bytes) basis, or word basis. Erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or  
whole chip basis.  
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read  
command can be issued to detect completion status of a program or erase operation via WIP bit.  
Advanced security features enhance the protection and security functions, please see security features section for  
more details.  
When the device is not in operation and CS# is high, it is put in standby mode.  
The MX25L12873G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after  
100,000 program and erase cycles.  
Table 1. Read performance Comparison  
Numbers  
of Dummy  
Cycles  
Dual Output Quad Output  
Dual IO  
Fast Read  
(MHz)  
Quad IO  
Fast Read  
(MHz)  
Quad I/O DT  
Read  
Fast Read  
(MHz)  
Fast Read  
(MHz)  
Fast Read  
(MHz)  
(MHz)  
4
6
-
-
-
80*  
54  
-
-
-
-
-
80*  
54*  
8
120*/133R  
-
120*/133R  
-
120*/133R  
-
120/133R  
-
84/104R  
120/133R  
70/80R  
84/100R  
10  
Notes:  
1. * mean default status.  
2. R mean VCC range = 3.0V-3.6V.  
P/N: PM2419  
Rev. 1.1, October 05, 2017  
5

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