Datasheet > MULTILYNX?CL2161

MULTILYNX?CL2161

更新时间： 2024-09-27 23:52:43

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
2页	89K
描述
MultiLynx?CL2161

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数据手册

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MULTILYNX?CL2161 数据手册

™

MultiLynx CL2161 Universal HFC

Interactive Cable Transceiver

OVERVI EW

The MultiLynx^™CL2161 is a universa l ca ble tra nsceiver solution for

a dva nced set-top boxes (STBs) a nd ca ble modems complia nt with DVB In-Ba nd,

DO CSIS, a nd EuroDO CSIS sta nda rds. The CL2161 is built for STB a nd ca ble

modem ma nufa cturers requiring the ma ximum performa nce with the lowest

system BO M cost. Its high level of integra tion provides ma nufa cturers with a

flexible, yet quick time-to-ma rket solution.

The CL2161 is a complete and highly integrated solution combining a Q AM

demodulator for downstream reception, a Q PSK/ 16-Q AM modulator for

upstream transmission, and a field-proven DO CSIS 1.0/ 1.1-compliant media

access controller (MAC).

The downstream channel provides full 16-256 Q AM demodulation and is

compliant with ITU J.83 Annex A and B and integrates a 10 bit A/ D converter.

The upstrea m Q PSK/ 16-Q AM burst tra nsmitter a long with ITU J.112 Annex A-,

B-complia nt FEC encoding provides a robust a nd cost-effective solution for

DO CSIS a pplica tions.

The hardware MAC (with packet parsing, filtering, and decryption), and the

two internal processors – an 88 MHz mini-RISC and 117 MHz SPARC v8

processor, upon which the standard specific MAC software is executed – allow

for flexible implementation of DVB In-Band, DO CSIS, or EuroDO CSIS standards.

The CL2161 ha s a full complement of low-speed periphera l interfa ce

devices including those commonly used on commercia l tuners such a s SPI,

inter-device communica tions (IDC), UART, a nd GPIO interfa ces.

CL2161

CPU and DSP

Bus

Interface

QAM

Demod

Unit

ADC

Diplexer

Tuner

DOCSIS

Pre

Process

Annex B FEC

Annex A FEC

Downstream

MAC

Processor

DES

Decoder

Copy/CRC

Engine

QPSK

Mod

VGA

FEC Encode

DOCSIS

MAC

DES

Encoder

Amp Control

SDRAM

Control

SPI

UART

GPIO

IDC

SDRAM

Th e

Co m m u n ica tio n s

™

High-Level Block Diagram of MultiLynx CL2161

Co m p a n y

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