Datasheet > MTBB0P10J3

MTBB0P10J3

更新时间： 2022-12-17 02:12:59

品牌	Logo	应用领域
全宇昕 - CYSTEKEC		/
页数	文件大小	规格书
7页	303K
描述
P-Channel Logic Level Enhancement Mode Power MOSFET

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数据手册

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MTBB0P10J3 数据手册

Spec. No. : C732J3

Issued Date : 2009.07.07

Revised Date :

CYStech Electronics Corp.

Page No. : 1/7

P-Channel Logic Level Enhancement Mode Power MOSFET

BVDSS

-100V

-10A

MTBB0P10J3

205mΩ

RDSON(MAX)

Features

• Low Gate Charge

• Simple Drive Requirement

• Pb-free lead plating & Halogen-free package

Equivalent Circuit

Outline

MTBB0P10J3

TO-252

G：Gate D：Drain

S：Source

G D S

Absolute Maximum Ratings (TC=25°C, unless otherwise noted)

Parameter

Symbol

Limits

Unit

Drain-Source Voltage

Gate-Source Voltage

Continuous Drain Current @ TC=25°C

Continuous Drain Current @ TC=100°C

Pulsed Drain Current *1

VDS

VGS

-100

±20

-10

-7

-40

-12

7.2

3.6

IDM

IAS

EAS

EAR

Avalanche Current

Avalanche Energy @ L=0.1mH, ID=-12A, RG=25Ω

Repetitive Avalanche Energy @ L=0.05mH *2

Total Power Dissipation @TC=25℃

Total Power Dissipation @TC=100℃

Operating Junction and Storage Temperature Range

-55~+175

Tj, Tstg

°C

Note : *1 Pulse width limited by maximum junction temperature

*2. Duty cycle ≤ 1%

MTBB0P10J3

CYStek Product Specification

12 3 4 5 6 7

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