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MT8926APR PDF预览

MT8926APR

更新时间: 2024-01-31 03:12:05
品牌 Logo 应用领域
美高森美 - MICROSEMI 电信电信集成电路
页数 文件大小 规格书
36页 808K
描述
SPECIALTY TELECOM CIRCUIT, PQCC28, PLASTIC, LCC-28

MT8926APR 技术参数

生命周期:Obsolete包装说明:QCCJ,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84JESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.505 mm
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
认证状态:Not Qualified座面最大高度:4.57 mm
标称供电电压:5 V表面贴装:YES
技术:CMOS电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:11.505 mm
Base Number Matches:1

MT8926APR 数据手册

 浏览型号MT8926APR的Datasheet PDF文件第1页浏览型号MT8926APR的Datasheet PDF文件第3页浏览型号MT8926APR的Datasheet PDF文件第4页浏览型号MT8926APR的Datasheet PDF文件第5页浏览型号MT8926APR的Datasheet PDF文件第6页浏览型号MT8926APR的Datasheet PDF文件第7页 
TM  
MT8926  
ISO-CMOS ST-BUS Family  
T1 Performance Monitoring  
Adjunct Circuit (PMAC)  
Data Sheet  
DS5718  
Issue 3  
July 1993  
Features  
ANSI T1.403 and T1.408 Performance  
Monitoring and Maintenance Functions  
Ordering Information  
MT8926AE  
MT8926AP  
28 Pin Plastic DIP  
28 Pin PLCC  
Operates in conjunction with Mitel's T1/ESF  
framer circuits (MT8976/77 and MH89760B)  
-40oC to +85oC  
D3/D4 (SF), and ESF modes of operation  
One and two second timers  
Supports bit-oriented and message-oriented  
data transfer over the Facility Data Link (FDL)  
Description  
ESF and D3/D4 Yellow Alarms, Alarm  
Indication Signal and Loss of Signal Indication  
The MT8926 Performance Monitoring Adjunct Circuit  
(PMAC) interworks with Mitel's MT8976/77 and  
MH89760B to provide performance monitoring data,  
alarms and T1 maintenance features.  
Framing Error, CRC Error and Bipolar Violation  
Error counters  
Alarm interrupts and counter overflow interrupts  
It meets the performance monitoring and maintenance  
requirements of ANSI T1.403 and T1.408, and also  
supports Channel Service Unit (CSU) requirements.  
Applications  
T1 line performance data collection  
CSU performance monitoring  
ISDN Primary Rate maintenance controller  
E8Ko  
FDLi  
E8Ki  
E8K/FDL  
Mux  
FDLo  
Transmit BOM  
Register  
FDL  
Extractor  
Receive BOM Register &  
RAI Debounce  
V
V
DD  
4 Bit SE  
Counter  
SEI  
FSI  
IRQ  
C2i  
Framer,  
SE/FE  
Detector  
4 Bit FE  
Counter  
CSTi0  
Snap-  
Shot  
Registers  
SS  
Line  
Loopback  
Integrator  
ST-BUS  
Interface  
CSTi1  
CSTo  
8 Bit BPV  
Counter  
BSI  
RxA  
B8ZS  
RESET  
Recovery,  
BPV Detector  
RxB  
ECLK  
8 Bit CRC  
Counter  
Payload  
& Line  
Loopback  
Control  
DSTi0  
DSTi1  
DSTo  
CSI  
AIS/LOS  
Detector  
Timer  
1SEC  
F0i  
Figure 1 - Functional Block Diagram  
SEMICMF.019  
1

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