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MT8889CE1 PDF预览

MT8889CE1

更新时间: 2024-09-27 05:50:35
品牌 Logo 应用领域
美高森美 - MICROSEMI 电信光电二极管电信集成电路
页数 文件大小 规格书
24页 513K
描述
DTMF Signaling Circuit, CMOS, PDIP20, LEAD FREE, PLASTIC, MS-001AD, DIP-20

MT8889CE1 数据手册

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MT8889C  
Integrated DTMF Transceiver  
with Adaptive Micro Interface  
Data Sheet  
July 2008  
Features  
Central office quality DTMF transmitter/receiver  
Ordering Information  
Low power consumption  
MT8889CE  
MT8889CS  
MT8889CN  
MT8889CE1  
MT8889CS1  
MT8889CN1  
MT8889CSR  
20 Pin PDIP  
20 Pin SOIC  
24 Pin SSOP  
20 Pin PDIP*  
20 Pin SOIC*  
24 Pin SSOP*  
20 Pin SOIC  
Tubes  
Tubes  
High speed adaptive micro interface  
Adjustable guard time  
Tubes  
Tubes  
Tubes  
Tubes  
Automatic tone burst mode  
Tape & Reel  
Tape & Reel  
MT8889CSR1 20 Pin SOIC*  
*Pb Free Matte Tin  
Call progress tone detection to -30 dBm  
-40°C to +85°C  
Applications  
Credit card systems  
Paging systems  
The receiver section is based upon the industry  
standard MT8870 DTMF receiver while the transmitter  
utilizes a switched capacitor D/A converter for low  
distortion, high accuracy DTMF signalling. Internal  
counters provide a burst mode such that tone bursts  
can be transmitted with precise timing. A call progress  
filter can be selected allowing a microprocessor to  
analyze call progress tones.  
Repeater systems/mobile radio  
Interconnect dialers  
Personal computers  
Description  
The MT8889C utilizes an adaptive micro interface,  
which allows the device to be connected to a number  
of popular microcontrollers with minimal external logic.  
The MT8889C is a monolithic DTMF transceiver with  
call progress filter. It is fabricated in CMOS technology  
offering low power consumption and high reliability.  
D0  
Data  
Bus  
Buffer  
Row and  
D/A  
Transmit Data  
D1  
D2  
D3  
Column  
TONE  
Converters  
Register  
Counters  
Status  
Register  
Interrupt  
Logic  
Tone Burst  
Gating Cct.  
Control  
Logic  
IRQ/CP  
Control  
Register  
A
IN+  
IN-  
GS  
+
-
Dial  
Tone  
Filter  
High Group  
Filter  
Digital  
DS/RD  
CS  
Algorithm  
and Code  
Converter  
Control  
Register  
B
I/O  
Low Group  
Filter  
Control  
OSC1  
OSC2  
Oscillator  
R/W/WR  
RS0  
Circuit  
Control  
Logic  
Receive Data  
Register  
Steering  
Logic  
Bias  
Circuit  
VDD VRef VSS  
ESt  
St/GT  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003-2008, Zarlink Semiconductor Inc. All Rights Reserved.  

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