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MT8812APR PDF预览

MT8812APR

更新时间: 2024-02-09 00:26:57
品牌 Logo 应用领域
美高森美 - MICROSEMI /
页数 文件大小 规格书
10页 328K
描述
Cross Point Switch, 1 Func, 12 Channel, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44

MT8812APR 技术参数

生命周期:Active零件包装代码:LPCC
包装说明:QCCJ,针数:44
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.22其他特性:8 X 12 ARRAY
模拟集成电路 - 其他类型:CROSS POINT SWITCHJESD-30 代码:S-PQCC-J44
JESD-609代码:e0长度:16.585 mm
信道数量:12功能数量:1
端子数量:44标称断态隔离度:95 dB
通态电阻匹配规范:5 Ω最大通态电阻 (Ron):220 Ω
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
认证状态:Not Qualified座面最大高度:4.57 mm
最大供电电压 (Vsup):14.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:16.585 mmBase Number Matches:1

MT8812APR 数据手册

 浏览型号MT8812APR的Datasheet PDF文件第2页浏览型号MT8812APR的Datasheet PDF文件第3页浏览型号MT8812APR的Datasheet PDF文件第4页浏览型号MT8812APR的Datasheet PDF文件第5页浏览型号MT8812APR的Datasheet PDF文件第6页浏览型号MT8812APR的Datasheet PDF文件第7页 
ISO-CMOS  
8 x 12 Analog Switch Array  
MT8812  
Data Sheet  
August 2005  
Features  
Internal control latches and address decoder  
Short set-up and hold times  
Ordering Information  
MT8812AE  
MT8812AP  
MT8812AP1  
40 Pin PDIP  
44 Pin PLCC  
44 Pin PLCC*  
Tubes  
Tubes  
Wide operating voltage: 4.5 V to 14.5 V  
14Vpp analog signal capability  
Tubes  
MT8812APR1 44 Pin PLCC*  
Tape & Reel  
Tubes  
MT8812AE1  
40 Pin PDIP*  
R
ON 65max. @ VDD=14V, 25°C  
*Pb Free Matte Tin  
RON 10@ VDD=14V, 25°C  
-0°C to +70°C  
Full CMOS switch for low distortion  
Minimum feedthrough and crosstalk  
Low power consumption ISO-CMOS technology  
Description  
The Zarlink MT8812 is fabricated in Zarlink’s ISO-  
CMOS technology providing low power dissipation and  
high reliability. The device contains a 8 x12 array of  
crosspoint switches along with a 7 to 96 line decoder  
and latch circuits. Any one of the 96 switches can be  
addressed by selecting the appropriate seven input  
bits. The selected switch can be turned on or off by  
applying a logical one or zero to the DATA input.  
Applications  
PBX systems  
Mobile radio  
Test equipment /instrumentation  
Analog/digital multiplexers  
Audio/Video switching  
STROBE  
DATA RESET  
VDD  
VSS  
1
1
AX0  
AX1  
AX2  
AX3  
AY0  
AY1  
AY2  
8 x 12  
Switch  
Array  
7 to 96  
Xi I/O  
Latches  
Decoder  
(i=0-11)  
96  
96  
• • • • • • • • • • • • • • • • • • •  
Yi I/O (i=0-7)  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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