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MT5C6405C-25L/XT PDF预览

MT5C6405C-25L/XT

更新时间: 2024-02-10 02:11:24
品牌 Logo 应用领域
AUSTIN 存储内存集成电路静态存储器
页数 文件大小 规格书
11页 77K
描述
16K x 4 SRAM SRAM MEMORY ARRAY

MT5C6405C-25L/XT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.92
最长访问时间:25 nsI/O 类型:COMMON
JESD-30 代码:R-XDIP-T24JESD-609代码:e0
内存密度:65536 bit内存集成电路类型:STANDARD SRAM
内存宽度:4端子数量:24
字数:16384 words字数代码:16000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:16KX4
输出特性:3-STATE封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP24,.3
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified最大待机电流:0.00025 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.12 mA标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MT5C6405C-25L/XT 数据手册

 浏览型号MT5C6405C-25L/XT的Datasheet PDF文件第2页浏览型号MT5C6405C-25L/XT的Datasheet PDF文件第3页浏览型号MT5C6405C-25L/XT的Datasheet PDF文件第4页浏览型号MT5C6405C-25L/XT的Datasheet PDF文件第5页浏览型号MT5C6405C-25L/XT的Datasheet PDF文件第6页浏览型号MT5C6405C-25L/XT的Datasheet PDF文件第7页 
SRAM  
MT5C6405  
Austin Semiconductor, Inc.  
PIN ASSIGNMENT  
16K x 4 SRAM  
SRAM MEMORY ARRAY  
(Top View)  
24-Pin DIP (C)  
(300 MIL)  
AVAILABLE AS MILITARY  
SPECIFICATIONS  
SMD 5962-86859  
A5  
A6  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Vcc  
A4  
• MIL-STD-883  
A7  
A3  
A8  
A2  
A9  
A1  
A10  
A11  
A12  
A13  
CE\ 10  
OE\ 11  
Vss 12  
A0  
FEATURES  
NC  
DQ4  
DQ3  
DQ2  
DQ1  
WE\  
• High Speed: 12, 15, 20, 25, 35, 45, 55, and 70ns  
• Battery Backup: 2V data retention  
• High-performance, low-power CMOS double-metal  
process  
• Single +5V (+10%) Power Supply  
• Easy memory expansion with CE\  
• All inputs and outputs are TTL compatible  
28-Pin LCC (EC)  
3
2 1 28 27  
OPTIONS  
• Timing  
MARKING  
26  
25  
24  
23  
22  
21  
20  
19  
18  
NC  
A4  
A3  
A2  
A1  
A0  
DQ4  
DQ3  
DQ2  
A6  
A7  
A8  
4
5
6
7
8
A9  
12ns access  
15ns access  
20ns access  
25ns access  
35ns access  
45ns access  
55ns access  
70ns access  
-12  
-15  
-20  
-25  
-35  
-45*  
-55*  
-70*  
A10  
A11  
A12  
A13  
CE\  
9
10  
11  
12  
13 14 15 16 17  
• Package(s)  
Ceramic DIP (300 mil)  
Ceramic LCC  
GENERAL DESCRIPTION  
C
E C  
No. 106  
No. 204  
The Austin Semiconductor SRAM family employs  
high-speed, low-power CMOS designs using a four-transistor  
memory cell. Austin Semiconductor SRAMs are fabricated  
using double-layer metal, double-layer polysilicon  
technology.  
• OperatingTemperature Ranges  
Industrial (-40oC to +85oC)  
Military (-55oC to +125oC)  
IT  
XT  
For flexibility in high-speed memory applications, Austin  
Semiconductor offers chip enable (CE\) and output enable  
(OE\) capability. These enhancements can place the outputs  
in High-Z for additional flexibility in system design.  
Writing to these devices is accomplished when write  
enable (WE\) and CE\ inputs are both LOW. Reading is  
accomplished when WE\ remains HIGH and CE\ and OE\ go  
LOW. The device offers a reduced power standby mode when  
disabled. This allows system designs to achieve low standby  
power requirements.  
• 2V data retention/low power  
L
*Electrical characteristics identical to those provided for the 35ns  
access devices.  
For more products and information  
please visit our web site at  
www.austinsemiconductor.com  
All devices operate from a single +5V power supply and  
all inputs and outputs are fully TTL compatible.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C6405  
Rev. 2.1 06/05  
1

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