Datasheet > MT5C1008LL

MT5C1008LL

更新时间： 2024-09-25 05:21:47

品牌	Logo	应用领域
AUSTIN		静态存储器
页数	文件大小	规格书
10页	124K
描述
128K x 8 SRAM WITH DUAL CHIP ENABLE ULTRA LOW POWER

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MT5C1008LL 数据手册

SRAM

MT5C1008(LL)

Austin Semiconductor, Inc.

128K x 8 SRAM

Ultra Low Power

PIN ASSIGNMENT

WITH DUAL CHIP ENABLE

(Top View)

ULTRA LOW POWER

32-Pin DIP (C)

AVAILABLE AS MILITARY

SPECIFICATIONS

•MIL-STD-883, para. 1.2.2 compliant

A16

A14

A12

VCC

A15

CE2

WE\

A13

FEATURES

• High Speed: 30 ns

• Low active power: 715 mW worst case

• Low CMOS standby power: 3.3 mW worst case

• 2.0V data retention, Ultra Low 0.3mW worst

case power dissipation

A11

OE\

A10

CE1\

I/O7

I/O6

I/O5

I/O4

I/O3

A2 10

A1 11

A0 12

• Battery backup applications

I/O0 13

I/O1 14

I/O2 15

GND 16

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE1\, CE2, and OE\ options

OPTIONS

• Timing

MARKING

30ns access

-30

GENERAL DESCRIPTION

• Package(s)

The MT5C1008 SRAM is a high-performance CMOS

static RAM organized as 131, 072 words by 8 bits, offering low

active power and ultra low standby and data retention current

levels. Easy memory expansion is provided by an active LOW

Chip Enable (CE1\), an active HIGH Chip Enable (CE2), and

active Low Output Enable (OE\), and three-state drivers.

Writing to the device is accomplished by taking Chip Enable

One (CE1\) and Write Enable (WE\) inputs LOW and Chip

Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0

through I/O7) is then written into the location specified on the

address pins (A0 through A16).

Ceramic DIP (400 mil)

No. 111

• Temperature

Military (-55°C to +125°C)

MIL

• Options

2V data retention/very low power LL

Reading from the device is accomplished by taking

Chip Enable One (CE₁\) and Output Enable (OE\) LOW while

forcing Write Enable (WE\) and Chip Enable Two (CE₂) HIGH.

Under these conditions, the contents of the memory location

specified by the address pins will appear on the I/O pins.

The eight input/output (I/O0 through I/O7) are placed

For more products and information

please visit our web site at

www.austinsemiconductor.com

in a high-impedance state when the device is deselected (CE1\)

HIGH or CE2 LOW), the outputs are disabled (OE\ HIGH), or

during a write operation (CE1\ LOW, CE2 HIGH, and WE\ LOW).

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

MT5C1008(LL)

Rev. 1.0 7/02

12 3 4 5 6 7...10

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与MT5C1008LL相关器件

型号	品牌	获取价格	描述	数据表
MT5C1008SOJ-100/XT	MICROSS	获取价格	Standard SRAM
MT5C1008SOJ-100L/883C	MICROSS	获取价格	Standard SRAM
MT5C1008SOJ-12	AUSTIN	获取价格	128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS
MT5C1008SOJ-12/883C	MICROSS	获取价格	Standard SRAM, 128KX8, 12ns, CMOS, CDSO32, CERAMIC, SOJ-32
MT5C1008SOJ-12/IT	MICROSS	获取价格	Standard SRAM, 128KX8, 12ns, CMOS, CDSO32, CERAMIC, SOJ-32
MT5C1008SOJ-12/XT	MICROSS	获取价格	Standard SRAM, 128KX8, 12ns, CMOS, CDSO32, CERAMIC, SOJ-32
MT5C1008SOJ-120/883C	MICROSS	获取价格	Standard SRAM
MT5C1008SOJ-120/IT	MICROSS	获取价格	Standard SRAM
MT5C1008SOJ-120/XT	MICROSS	获取价格	Standard SRAM
MT5C1008SOJ-120L/883C	MICROSS	获取价格	Standard SRAM

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