Datasheet > MT58L256L18F1B-6.8

MT58L256L18F1B-6.8

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	349K
描述
Standard SRAM, 256KX18, 6.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119

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4Mb : 256K x 18, 128K x 32/36

FLOW-THROUGH SYNCBURST SRAM

FBGA PIN DESCRIPTIONS

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

SA0

SA1

Input Synchronous Address Inputs: These inputs are registered and must

meet the setup and hold times around the rising edge of CLK.

2A, 2B, 3P,

3R, 4P, 4R,

2A, 2B, 3P,

3R, 4P, 4R,

8P, 8R, 9P, 9R, 8P, 8R, 9P,

10A, 10B, 10P, 9R, 10A, 10B,

10R, 11A, 11R 10P, 10R, 11R

–

BWa#

BWb#

BWc#

BWd#

Input Synchronous Byte Write Enables: These active LOW inputs allow

individual bytes to be written and must meet the setup and hold

times around the rising edge of CLK. A byte write enable is LOW

for a WRITE cycle and HIGH for a READ cycle. For the x18 version,

BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For

the x32 and x36 versions, BWa# controls DQas and DQPa; BWb#

controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#

controls DQds and DQPd. Parity is only available on the x18 and x36

versions.

–

BWE#

GW#

CLK

Input Byte Write Enable: This active LOW input permits BYTE WRITE

operations and must meet the setup and hold times around the

rising edge of CLK.

Input Global Write: This active LOW input allows a full 18-, 32-, or 36-bit

WRITE to occur independent of the BWE# and BWx# lines and must

meet the setup and hold times around the rising edge of CLK.

Input Clock: This signal registers the address, data, chip enable, byte write

enables, and burst control inputs on its rising edge. All synchronous

inputs must meet setup and hold times around the clock’s rising

edge.

CE#

CE2#

Input Synchronous Chip Enable: This active LOW input is used to enable

the device and conditions the internal use of ADSP#. CE# is sampled

only when a new external address is loaded.

Input Synchronous Chip Enable: This active LOW input is used to enable

the device and is sampled only when a new external address is

loaded.

11H

Input Snooze Enable: This active HIGH, asynchronous input causes the

device to enter a low-power standby mode in which all data in the

memory array is retained. When ZZ is active, all other inputs are

ignored.

CE2

Input Synchronous Chip Enable: This active HIGH input is used to enable

the device and is sampled only when a new external address is

loaded.

OE#(G#)

ADV#

Input Output Enable: This active LOW, asynchronous input enables the

data I/O output drivers.

Input Synchronous Address Advance: This active LOW input is used to

advance the internal burst counter, controlling burst access after the

external address is loaded. A HIGH on ADV# effectively causes wait

states to be generated (no address advance). To ensure use of

correct address during a WRITE cycle, ADV# must be HIGH at the

rising edge of the first clock after an ADSP# cycle is initiated.

(continued on next page)

4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

MT58L256L18F1_D.p65 – Rev. 10/01

1...5 6 789 10 11...31

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与MT58L256L18F1B-6.8相关器件

型号	品牌	获取价格	描述	数据表
MT58L256L18F1B-7.5	CYPRESS	获取价格	Standard SRAM, 256KX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119
MT58L256L18F1B-8.5	CYPRESS	获取价格	Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119
MT58L256L18F1B-8.5IT	CYPRESS	获取价格	Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119
MT58L256L18F1F-10	CYPRESS	获取价格	Cache SRAM, 256KX18, 10ns, CMOS, PBGA165, FBGA-165
MT58L256L18F1F-10IT	CYPRESS	获取价格	Standard SRAM, 256KX18, 10ns, CMOS, PBGA165, FBGA-165
MT58L256L18F1F-6.8	CYPRESS	获取价格	Cache SRAM, 256KX18, 6.8ns, CMOS, PBGA165, FBGA-165
MT58L256L18F1F-7.5	CYPRESS	获取价格	Cache SRAM, 256KX18, 7.5ns, CMOS, PBGA165, FBGA-165
MT58L256L18F1F-7.5IT	CYPRESS	获取价格	Standard SRAM, 256KX18, 7.5ns, CMOS, PBGA165, FBGA-165
MT58L256L18F1F-8.5	CYPRESS	获取价格	Cache SRAM, 256KX18, 8.5ns, CMOS, PBGA165, FBGA-165
MT58L256L18F1F-8.5IT	CYPRESS	获取价格	Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA165, FBGA-165

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