4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
4Mb SYNCBURST™
SRAM
MT58L256L18P1, MT58L128L32P1,
MT58L128L36P1; MT58L256V18P1,
MT58L128V32P1, MT58L128V36P1
3.3V VDD, 3.3V or 2.5V I/O, Pipelined, Single-Cycle
Deselect
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (VDD
1
100-PINTQFP
)
• Separate +3.3V or +2.5V isolated output buffer
supply (VDDQ)
• SNOOZE MODE for reduced-power standby
• Single-cycle deselect (Pentium® BSRAM-compatible)
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL WRITE
• Three chip enables for simple depth expansion
and address pipelining
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down for portable applications
• 165-pin FBGA package
165-BALLFBGA
• 100-pin TQFP package
• Low capacitive bus loading
• x18, x32, and x36 versions available
OPTIONS
MARKING
• Timing (Access/Cycle/MHz)
2.6ns/4.4ns/225 MHz
2.8ns/5ns/200 MHz
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
-4.4
-5
-6
-7.5
-10
NOTE: 1. JEDEC-standardMS-026BHA(LQFP).
• Configurations
3.3V I/O
256K x 18
128K x 32
128K x 36
2.5V I/O
MT58L256L18P1
MT58L128L32P1
MT58L128L36P1
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
256K x 18
128K x 32
128K x 36
MT58L256V18P1
MT58L128V32P1
MT58L128V36P1
GENERALDESCRIPTION
• Packages
The Micron® SyncBurst™ SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
100-pin TQFP
165-pin FBGA
T
F*
• Operating Temperature Range
Commercial (0°C to +70°C)
Micron’s 4Mb SyncBurst SRAMs integrate a
256K x 18, 128K x 32, or 128K x 36 SRAM core with ad-
vanced synchronous peripheral circuitry and a 2-bit
burst counter. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input (CLK). The synchronous inputs include all
addresses, all data inputs, active LOW chip enable
None
IT
Industrial (-40°C to +85°C)**
Part Number Example:
MT58L256L18P1T-6
4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
©2003,MicronTechnology,Inc.
1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.