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MT3171BE1

更新时间： 2024-02-05 16:21:03
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信集成电路电信信令电路电信电路光电二极管
页数 文件大小 规格书
15页 488K
描述
Wide Dynamic Range DTMF Receiver

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MT3171BE1 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：DIP, DIP8,.3Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.74
JESD-30 代码：R-PDIP-T8JESD-609代码：e3
长度：9.59 mm功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP8,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：260电源：5 V
认证状态：Not Qualified座面最大高度：5.33 mm
子类别：Telecom Signaling Circuits最大压摆率：0.008 mA
标称供电电压：5 V表面贴装：NO
电信集成电路类型：DTMF SIGNALING CIRCUIT温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：7.62 mm
Base Number Matches：1

MT3171BE1 数据手册

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MT3170B/71B, MT3270B/71B, MT3370B/71B  
Data Sheet  
Description  
The MT3x7xB is a family of high performance DTMF receivers which decode all 16 tone pairs into a 4-bit binary  
code. These devices incorporate an AGC for wide dynamic range and are suitable for end-to-end signalling. The  
MT3x70B provides an early steering (ESt) logic output to indicate the detection of a DTMF signal and requires  
external software guard time to validate the DTMF digit. The MT3x71B, with preset internal guard times, uses a  
delay steering (DStD) logic output to indicate the detection of a valid DTMF digit. The 4-bit DTMF binary digit can be  
clocked out synchronously at the serial data (SD) output. The SD pin is multiplexed with call progress detector  
output. In the presence of supervisory tones, the call progress detector circuit indicates the cadence (i.e., envelope)  
of the tone burst. The cadence information can then be processed by an external microcontroller to identify specific  
call progress signals. The MT327xB and MT337xB can be used with a crystal or a ceramic resonator without  
additional components. A power-down option is provided for the MT317xB and MT337xB.  
MT3370B/71B  
MT3170B/71B  
MT3270B/71B  
MT3370B/71B  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
2
NC  
NC  
NC  
18  
17  
16  
15  
14  
13  
12  
11  
10  
1
2
3
4
5
6
7
8
9
NC  
INPUT  
PWDN  
OSC2  
NC  
VDD  
NC  
NC  
INPUT  
PWDN  
CLK  
VDD INPUT  
VDD  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
INPUT  
PWDN  
NC  
3
4
5
VDD  
NC  
NC  
ESt/  
ESt/  
OSC2  
DStD  
ESt/DStD  
NC  
ESt/DStD  
NC  
DStD  
6
7
OSC2  
OSC1  
VSS  
OSC1  
ACK  
ACK  
OSC1  
NC  
ACK  
NC  
ACK  
SD  
8
VSS  
VSS  
SD  
SD  
NC  
SD  
9
NC  
NC  
VSS  
NC  
NC  
10  
NC  
8 PIN PLASTIC DIP  
18 PIN PLASTIC SOIC  
20 PIN SSOP  
Figure 2 - Pin Connections  
Pin Description  
Pin #  
327xB  
Name  
Description  
337xB  
317xB  
2
4
6
1
2
3
1
-
3
INPUT DTMF/CP Input. Input signal must be AC coupled via capacitor.  
OSC2 Oscillator Output.  
OSC1 Oscillator/Clock Input. This pin can either be driven by:  
(CLK) 1) an external digital clock with defined input logic levels. OSC2  
should be left open.  
2) connecting a crystal or ceramic resonator between OSC1 and  
OSC2 pins.  
9
11  
4
5
4
5
VSS  
SD  
Ground. (0V)  
Serial Data/Call Progress Output. This pin serves the dual function  
of being the serial data output when clock pulses are applied after  
validation of DTMF signal, and also indicates the cadence of call  
progress input. As DTMF signal lies in the same frequency band as  
call progress signal, this pin may toggle for DTMF input. The SD pin  
is at logic low in powerdown state.  
13  
6
6
ACK  
Acknowledge Pulse Input. After ESt or DStD is high, applying a  
sequence of four pulses on this pin will then shift out four bits on the  
SD pin, representing the decoded DTMF digit. The rising edge of the  
first clock is used to latch the 4-bit data prior to shifting. This pin is  
pulled down internally. The idle state of the ACK signal should be  
low.  
2
Zarlink Semiconductor Inc.  
1234567...15

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