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MSP430F2011TRSA PDF预览

MSP430F2011TRSA

更新时间: 2024-02-09 12:24:20
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路时钟
页数 文件大小 规格书
92页 1795K
描述
MIXED SIGNAL MICROCONTROLLER

MSP430F2011TRSA 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:QFN-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01Factory Lead Time:6 weeks
风险等级:0.85Is Samacsys:N
具有ADC:YES其他特性:IT ALSO OPERATES AT 1.8 V AT 6 MHZ
地址总线宽度:位大小:16
边界扫描:YESCPU系列:MSP430
最大时钟频率:16 MHzDAC 通道:NO
DMA 通道:NO外部数据总线宽度:
格式:FIXED POINT集成缓存:NO
JESD-30 代码:S-PQCC-N16JESD-609代码:e4
长度:4 mm低功率模式:YES
湿度敏感等级:2DMA 通道数量:
I/O 线路数量:10串行 I/O 数:
端子数量:16计时器数量:2
片上数据RAM宽度:8片上程序ROM宽度:8
最高工作温度:105 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC16,.16SQ,25
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:2/3.3 V
认证状态:Not QualifiedRAM(字节):128
RAM(字数):0.125ROM(单词):2048
ROM可编程性:FLASH座面最大高度:1 mm
速度:16 MHz子类别:Microcontrollers
最大压摆率:0.37 mA最大供电电压:3.6 V
最小供电电压:1.8 V标称供电电压:2.2 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

MSP430F2011TRSA 数据手册

 浏览型号MSP430F2011TRSA的Datasheet PDF文件第6页浏览型号MSP430F2011TRSA的Datasheet PDF文件第7页浏览型号MSP430F2011TRSA的Datasheet PDF文件第8页浏览型号MSP430F2011TRSA的Datasheet PDF文件第10页浏览型号MSP430F2011TRSA的Datasheet PDF文件第11页浏览型号MSP430F2011TRSA的Datasheet PDF文件第12页 
MSP430F20x3  
MSP430F20x2  
MSP430F20x1  
www.ti.com  
SLAS491H AUGUST 2005REVISED AUGUST 2011  
Table 3. Terminal Functions, MSP430F20x2  
TERMINAL  
NO.  
PW, N  
DESCRIPTION  
NAME  
I/O  
RSA  
General-purpose digital I/O pin  
Timer_A, clock signal TACLK input  
ACLK signal output  
P1.0/TACLK/ACLK/A0  
2
1
I/O  
ADC10 analog input A0  
General-purpose digital I/O pin  
P1.1/TA0/A1  
P1.2/TA1/A2  
3
4
2
3
I/O  
I/O  
Timer_A, capture: CCI0A input, compare: Out0 output  
ADC10 analog input A1  
General-purpose digital I/O pin  
Timer_A, capture: CCI1A input, compare: Out1 output  
ADC10 analog input A2  
General-purpose digital I/O pin  
ADC10 conversion clock output  
ADC10 analog input A3  
Input for negative external reference voltage/negative internal reference voltage  
output  
P1.3/ADC10CLK/A3/  
VREF-/VeREF-  
5
6
4
5
I/O  
General-purpose digital I/O pin  
SMCLK signal output  
ADC10 analog input A4  
Input for positive external reference voltage/positive internal reference voltage  
output  
P1.4/SMCLK/A4/VREF+/  
VeREF+/TCK  
I/O  
JTAG test clock, input terminal for device programming and test  
General-purpose digital I/O pin  
Timer_A, compare: Out0 output  
P1.5/TA0/A5/SCLK/TMS  
7
8
6
7
I/O  
I/O  
ADC10 analog input A5  
USI: external clock input in SPI or I2C mode; clock output in SPI mode  
JTAG test mode select, input terminal for device programming and test  
General-purpose digital I/O pin  
Timer_A, capture: CCI1B input, compare: Out1 output  
ADC10 analog input A6  
USI: Data output in SPI mode; I2C clock in I2C mode  
JTAG test data input or test clock input during programming and test  
P1.6/TA1/A6/SDO/SCL/  
TDI/TCLK  
General-purpose digital I/O pin  
P1.7/A7/SDI/SDA/  
TDO/TDI(1)  
ADC10 analog input A7  
USI: Data input in SPI mode; I2C data in I2C mode  
JTAG test data output terminal or test data input during programming and test  
9
8
I/O  
I/O  
Input terminal of crystal oscillator  
General-purpose digital I/O pin  
Timer_A, compare: Out1 output  
XIN/P2.6/TA1  
13  
12  
Output terminal of crystal oscillator  
General-purpose digital I/O pin(2)  
XOUT/P2.7  
12  
10  
11  
9
I/O  
I
Reset or nonmaskable interrupt input  
Spy-Bi-Wire test data input/output during programming and test  
RST/NMI/SBWTDIO  
Selects test mode for JTAG pins on Port 1. The device protection fuse is  
connected to TEST.  
TEST/SBWTCK  
11  
10  
I
Spy-Bi-Wire test clock input during programming and test  
VCC  
1
NA  
NA  
16  
Supply voltage  
VSS  
14  
Ground reference  
DVCC  
AVCC  
DVSS  
AVSS  
QFN Pad  
NA  
NA  
NA  
NA  
NA  
Digital supply voltage  
15  
Analog supply voltage  
14  
Digital ground reference  
Analog ground reference  
QFN package pad. Connection to VSS is recommended.  
13  
Pad  
NA  
(1) TDO or TDI is selected via JTAG instruction.  
(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to  
this pad after reset.  
Copyright © 20052011, Texas Instruments Incorporated  
9

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