Datasheet > MR82C237

MR82C237

更新时间： 2024-02-12 14:52:39

品牌	Logo	应用领域
英特矽尔 - INTERSIL		控制器
页数	文件大小	规格书
25页	161K
描述
CMOS High Performance Programmable DMA Controller

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技术参数
数据手册

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MR82C237 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	CERAMIC, LCC-44
针数：	44	Reach Compliance Code：	not_compliant
ECCN代码：	3A001.A.2.C	HTS代码：	8542.31.00.01
风险等级：	5.92	地址总线宽度：	8
总线兼容性：	80C286; 80286; 80186; 80C86; 8086; 80C88; 8088; 8085; Z80; NSC800	最大时钟频率：	8 MHz
外部数据总线宽度：	8	JESD-30 代码：	S-CQCC-N44
JESD-609代码：	e0	长度：	16.535 mm
DMA 通道数量：	4	端子数量：	44
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QCCN
封装等效代码：	LCC44,.65SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
筛选级别：	38535Q/M;38534H;883B	座面最大高度：	3.05 mm
子类别：	DMA Controllers	最大压摆率：	16 mA
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	16.535 mm
uPs/uCs/外围集成电路类型：	DMA CONTROLLER

MR82C237 数据手册

82C237

Pin Description (Continued)

SYMBOL

NUMBER

TYPE

DESCRIPTION

EOP

I/O

END OF PROCESS: End of Process (EOP) is an active low bidirectional signal. Information

concerning the completion of DMA services is available at the bidirectional EOP pin.

The 82C237 allows an external signal to terminate an active DMA service by pulling the EOP pin

low. A pulse is generated by the 82C237 when terminal count (TC) for any channel is reached,

except for channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will

be output when the TC for channel 1 occurs.

The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor

to V

When an EOP pulse occurs, whether internally or externally generated, the 82C237 will terminate

the service, and if autoinitialize is enabled, the base registers will be written to the current registers

of that channel. The mask bit and TC bit in the status word will be set for the currently active channel

by EOP unless the channel is programmed for autoinitialize. In that case, the mask bit remains clear.

A0-A3

32-35

I/O

ADDRESS: The four least signiﬁcant address lines are bidirectional three-state signals. In the Idle

cycle, they are inputs and are used by the 82C237 to address the control register to be loaded or

read. In the Active cycle, they are outputs and provide the lower 4-bits of the output address. When

in 16-bit mode (82C237 only), and the active channel is a 16-bit channel (as deﬁned by the Data-

Width register), then A0 will remain low during the entire transfer (i.e. an even word address will al-

ways be generated).

A4-A7

HRQ

37-40

ADDRESS: The four most signiﬁcant address lines are three-state outputs and provide 4-bits of

address. These lines are enabled only during the DMA service.

HOLD REQUEST: The Hold Request (HRQ) output is used to request control of the system bus.

When a DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made,

the 82C237 issues HRQ. The HLDA signal then informs the controller when access to the system

busses is permitted. For stand-alone operation where the 82C237 always controls the busses, HRQ

may be tied to HLDA. This will result in one S0 state before the transfer.

DACK0-

DACK3

14, 15

24, 25

DMA ACKNOWLEDGE: DMA acknowledge is used to notify the individual peripherals when one

has been granted a DMA cycle. The sense of these lines is programmable. RESET initializes them

to active low.

AEN

ADDRESS ENABLE: Address Enable enables the 8-bit latch containing the upper 8 address bits

onto the system address bus. AEN can also be used to disable other system bus drivers during DMA

transfers. AEN is active HIGH.

ADSTB

ADDRESS STROBE: This is an active high signal used to control latching of the upper address

byte. It will drive directly the strobe input of external transparent octal latches, such as the 82C82.

During block operations, ADSTB will only be issued when the upper address byte must be updated,

thus speeding operation through elimination of S1 states. ADSTB timing is referenced to the falling

edge of the 82C237 clock.

MEMR

MEMW

DWLE

MEMORY READ: The Memory Read signal is an active low three-state output used to access data

from the selected memory location during a DMA Read or a memory-to-memory transfer.

MEMORY WRITE: The Memory Write is an active low three-state output used to write data to the

selected memory location during a DMA Write or a memory-to-memory transfer.

DATA-WIDTH, LATCH ENABLE: In normal 8-bit transfer mode (16-bit transfer mode not enabled),

this output is always high impedance three-stated. In 16-bit transfer mode (82C237 only), this output

serves a dual purpose. During S1 cycles, the DWLE output indicates the data width (0 = 16-bit, 1 =

8-bit) of the active channel. During memory-to-memory transfers, the DWLE output is used to enable

an external latch which temporarily stores the 8 most signiﬁcant bits of data during the read-from-

memory transfer. DWLE enables this byte of data onto the data bus during the write-to-memory

transfer of a memory-to-memory operation.

4-151

1 2 345 6 7...25

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MR82C237-12	INTERSIL	CMOS High Performance Programmable DMA Controller	获取价格
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