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MPC5602DXLL PDF预览

MPC5602DXLL

更新时间: 2024-02-17 15:01:13
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 闪存控制器
页数 文件大小 规格书
77页 675K
描述
Up to 256 KB on-chip Code Flash supported with Flash controller and ECC

MPC5602DXLL 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.64具有ADC:YES
其他特性:ALSO OPERATES AT 3 V MINIMUM SUPPLY地址总线宽度:
位大小:32最大时钟频率:16 MHz
DAC 通道:NODMA 通道:YES
外部数据总线宽度:JESD-30 代码:S-PQFP-G100
长度:14 mmI/O 线路数量:79
端子数量:100最高工作温度:105 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
认证状态:Not QualifiedROM可编程性:FLASH
座面最大高度:1.7 mm速度:48 MHz
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

MPC5602DXLL 数据手册

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Freescale Semiconductor  
Data Sheet: Advance Information  
Document Number: MPC5602D  
Rev. 3.1, 02/2011  
MPC5602D  
100 LQFP  
14 mm x 14 mm  
64 LQFP  
10 mm x 10 mm  
MPC5602D Microcontroller  
Data Sheet  
Single issue, 32-bit CPU core complex (e200z0)  
Real Time Counter (RTC) with clock source from  
128 kHz or 16 MHz internal RC oscillator  
supporting autonomous wakeup with 1 ms  
resolution with max timeout of 2 seconds  
®
— Compliant with the Power Architecture  
embedded category  
— Includes an instruction set enhancement  
allowing variable length encoding (VLE) for  
code size footprint reduction. With the optional  
encoding of mixed 16-bit and 32-bit  
Up to 4 periodic interrupt timers (PIT) with 32-bit  
counter resolution  
1 System Module Timer (STM)  
instructions, it is possible to achieve significant  
code size footprint reduction.  
Nexus development interface (NDI) per IEEE-ISTO  
5001-2003 Class 1 standard  
Up to 256 KB on-chip Code Flash supported with  
Flash controller and ECC  
Device/board boundary Scan testing supported with  
per Joint Test Action Group (JTAG) of IEEE (IEEE  
1149.1)  
64 KB on-chip Data Flash with ECC  
Up to 16 KB on-chip SRAM with ECC  
On-chip voltage regulator (VREG) for regulation of  
input supply for all internal levels  
Interrupt controller (INTC) with multiple interrupt  
vectors, including 20 external interrupt sources and  
18 external interrupt/wakeup sources  
Frequency modulated phase-locked loop (FMPLL)  
Crossbar switch architecture for concurrent access to  
peripherals, Flash, or SRAM from multiple bus  
masters  
Boot assist module (BAM) supports internal Flash  
programming via a serial link (CAN or SCI)  
Timer supports input/output channels providing a  
range of 16-bit input capture, output compare, and  
pulse width modulation functions (eMIOS-lite)  
Up to 33 channel 12-bit analog-to-digital converter  
(ADC)  
2 serial peripheral interface (DSPI) modules  
3 serial communication interface (LINFlex) modules  
1 enhanced full CAN (FlexCAN) module with  
configurable buffers  
Up to 79 configurable general purpose pins  
supporting input and output operations (package  
dependent)  
This document contains information on a new product. Specifications and information herein  
are subject to change without notice.  
© Freescale Semiconductor, Inc., 2009, 2010. All rights reserved.  
Preliminary—Subject to Change Without Notice  

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