MP7652

更新时间： 2024-01-08 19:14:34

品牌	Logo	应用领域
艾科嘉 - EXAR		转换器数模转换器
页数	文件大小	规格书
16页	181K
描述
4-Channel Voltage Output 15 MHz, Input Bandwidth, 8-Bit Multiplying DACs with 3-Wire Serial Digital Port and Independent References

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MP7652 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOP, SOP24,.4
针数：	24	Reach Compliance Code：	unknown
风险等级：	5.92	Is Samacsys：	N
最大模拟输出电压：	3 V	转换器类型：	D/A CONVERTER
输入位码：	BINARY	输入格式：	SERIAL
JESD-30 代码：	R-PDSO-G24	JESD-609代码：	e0
长度：	15.4 mm	最大线性误差 (EL)：	0.3906%
标称负供电电压：	-5 V	位数：	8
功能数量：	4	端子数量：	24
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP24,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	+-5 V
认证状态：	Not Qualified	座面最大高度：	2.65 mm
标称安定时间 (tstl)：	0.275 µs	子类别：	Other Converters
标称供电电压：	5 V	表面贴装：	YES
技术：	BICMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	7.5 mm	Base Number Matches：	1

MP7652 数据手册

MP7652

THEORY OF OPERATION

The MP7652 is a 4-channel multiplying D/A converter that in-

corporates a novel open loop architecture invented by MPS.

Thedesignproducesthewidestbandwidth, fastestsettlingtime,

most constant group delay, and a very low noise operation

compared to the conventional R-2R based architectures (given

an equal technology platform). This device is particularly useful

in applications where analog multipliers are used to perform the

gainadjustment function for high frequency analog signal condi-

tioning. Analog multipliers produce much higher noise and.

This design allows for digital control of gain with constant and

very low noise for all gain settings.

going low also disables the serial data input (SDI), output (SDO

tri-stated) and the CLK input. This design tremendously re-

duces digital noise, and glitch transients into the DACs due to

free running CLK and SDI. Also, tri-stating the SDO output with

LD signal would allow read back of pre-stored digital data of the

selected package using one SDO wire for all DAC ICs on the

board. When the PRESET signal is low, the output of all DACs

are 1/2 of (V_REFP+ V_REFN), regardless of any digital inputs.

Note that V_REFPis referenced to V_REFN

Power Supplies and Voltage Reference DC Voltage

Ranges

Linearity Characteristics

For the single supply operation, V_CC= +10 V, V_DD= +5 V, and

_EE= DGND = 0 V. The V_O1-4 and V_REFP1-4 range would be

Each DAC achieves DNL ꢀ +0.5 LSB (typ), INL ꢀ +1 LSB

(typ), and gain error ꢀ +1.5%. Since all 4 channel D/A convert-

ers are fabricated on the same IC, the linearity matching and

gain matching of +0.5% (typ) is achieved.

V_CC–1.8 V (10 – 1.8 = 8.2 V) to V_EE+1.5 V (0 + 1.5 = 1.5 V).

_REFNis the equivalent of AGND for this DAC. In this mode

_REFNcan be set at (V_CC+ V_EE)/2 = (10 + 0)/2 = 5 V. V_REFN1-4

DC range can also be set from V_EE+1.5 = 1.5 V to V_CC– 1.5 =

8.2 V. Refer to Table 2. for the relationship equations.

AC and Low Noise Performance

For the dual supply operation, V_CC= +5, V_DD= +5, and V_EE

The novel subranging architecture delivers a 15 MHz (type)

–3 dB bandwidth. A constant group delay of 70 ns (typ) is

achieved to frequencies up to 8 MHz. Analog output settling

time for a code change of FS to ZS and ZS to FS with V_REFP= 3

V, is typically 150 ns (with R_L= 5 k to V_EE). Also, with all codes

set to FS (all 1s) and a V_REFP3 V step, the analog output will

settle to 8 bits in less than 110 ns (typ). Note that the AC perfor-

mance specifications also match to between all 4 channels. The

above AC and transient performance is achieved with each

channel consuming only 20 mW (typ) with 10 V p-p supplies.

–5 V. The V_OUT1-4 and V_REFP1-4 range would be V_CC–1.8 V

(–1.8 = 3.2 V) to V_EE+1.5 V (–5 + 1.5 = –3.5 V). In this mode

V_REFNcan be set to (V_CC+ V_EE)/2 = (5 – 5)/2 = 0 V. Similarly,

_REFN1-4 DC range can be set from V_EE+1.5 V = 3.5 V to V_CC

–1.8 = +3.2 V. Refer to Table 2. for the relationship equations.

1-4

REFP

OUT

1-4

Serial Port

DAC

Q2 Q1

MP7652 is equipped with a serial data 3-wire standard µ-proc-

essor logic interface to reduce pin count, package size, and

board wire (space). This interface consists of LD which controls

the transfer of data to the selected DAC channel, SDI (serial

data/address input), CLK (shift register clock) and SDO (serial

data output). When the LD signal is high, CLK signal loads the

digital input bits (SDI) into the 12-bit shift register. The LD signal

going low loads this data into the selected DAC. The LD signal

REFN

Figure 4. Simplified Block Diagram

Rev. 1.00

1...4 5 678 9 10...16

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与MP7652相关器件

型号	品牌	描述	获取价格	数据表
MP7652AN	EXAR	4-Channel Voltage Output 15 MHz, Input Bandwidth, 8-Bit Multiplying DACs with 3-Wire Seria	获取价格
MP7652AS	EXAR	4-Channel Voltage Output 15 MHz, Input Bandwidth, 8-Bit Multiplying DACs with 3-Wire Seria	获取价格
MP7670	EXAR	8-CHANNEL, VOLTAGE OUTPUT, 5 MHZ, 4 QUADRANT MULTIPLYING 8BIT D/A CONVERTER WITH SERIAL DI	获取价格
MP7670AN	EXAR	8-CHANNEL, VOLTAGE OUTPUT, 5 MHZ, 4 QUADRANT MULTIPLYING 8BIT D/A CONVERTER WITH SERIAL DI	获取价格
MP7670AS	EXAR	8-CHANNEL, VOLTAGE OUTPUT, 5 MHZ, 4 QUADRANT MULTIPLYING 8BIT D/A CONVERTER WITH SERIAL DI	获取价格
MP7680	EXAR	5 V CMOS 12-Bit Quad Double-Buffered Multiplying Digital-to-Analog Converter	获取价格

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