MP3318–3-CHANNEL, LINEAR/EXPONENTIAL DIMMING, WLED DRIVER W/ I2C
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.6V, VEN = VPWM = high, typical values are at TA = 25°C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Unit
Rise time of SCLH clock
tR,SCL
10
40
ns
Rise time of SCLH clock after
repeated start and
tR,SCL1
10
80
ns
acknowledge bit
Fall time of SCLH clock
Rise time of SDAH data
Fall time of SDAH data
Setup time for stop condition
tF,SCL
tR,SDA
tF,SDA
tSU,STO
10
10
40
80
80
ns
ns
ns
ns
10
160
Capacitive load for SDAH line
and SCLH line
(8)
CB
100
400
pF
Capacitive load for
SDAH+SDA line and
SCLH+SCL line
CB
pF
NOTES:
5) Matching is defined as the difference between the maximum to minimum current divided by 2x the average currents.
6) Guaranteed by design.
7) A device must internally provide a data hold time to bridge the underfined part between VIL and VIH of the falling edge of the SCLH signal.
An input circuit with a threshold as low as possible for the falling edge of SCLH signal minimizes the hold time.
8) For the bus line load CB between 100 and 400pF the timing parameters must be increased linearly.
P
Sr
tF,SDA
tR,SDA
SDAH
SCLH
tSU,SDA
tHD,SDA
tHIGH
tSU,STA
tHD,STA
tSU,STA
tLOW
tLOW
tHIGH
Sr
tR,SCL1
tR,SCL
tR,SCL1
tF,SCL
Sr: Repeated START Condition
P: STOP Condition
I2C-Compatible Interface Timing Diagram
MP3318 Rev.1.0
10/17/2017
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