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MMDP-67204FV-15 PDF预览

MMDP-67204FV-15

更新时间: 2023-02-15 00:00:00
品牌 Logo 应用领域
TEMIC 先进先出芯片
页数 文件大小 规格书
20页 344K
描述
FIFO, 4KX9, 15ns, Asynchronous, CMOS, CDFP28, 0.400 INCH, FP-28

MMDP-67204FV-15 数据手册

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Features  
First-in first-out dual port memory  
4096 y 9 organisation  
Fast Flag and access times: 15, 30 ns  
Wide temperature range: - 55°C to + 125°C  
Fully expandable by word width or depth  
Asynchronous read/write operations  
Empty, full and half flags in single device mode  
Retransmit capability  
Bi-directional applications  
Battery back-up operation: 2V data retention  
TTL compatible  
Single 5V + 10% power supply  
QML Q and V with SMD 5962-89568  
Rad Tolerant  
High Speed  
4 K x 9  
Description  
The M67204F implements a first-in first-out algorithm, featuring asynchronous  
read/write operations. The FULL and EMPTY flags prevent data overflow and under-  
flow. The Expansion logic allows unlimited expansion in word size and depth with no  
timing penalties. Twin address pointers automatically generate internal read and write  
addresses, and no external address information are required for the Atmel FIFOs.  
Address pointers are automatically incremented with the write pin and read pin. The 9  
bits wide data are used in data communications applications where a parity bit for  
error checking is necessary. The Retransmit pin reset the Read pointer to zero without  
affecting the write pointer. This is very useful for retransmitting data when an error is  
detected in the system.  
Parallel FIFO  
M67204F  
Using an array of eight transistors (8 T) memory cell, the M67204F combine an  
extremely low standby supply current (typ = 0.1 µA) with a fast access time at 15 ns  
over the full temperature range. All versions offer battery backup data retention capa-  
bility with a typical power consumption at less than 2 µW.  
The M67204F is processed according to the methods of the latest revision of the MIL  
PRF 38535 (Q and V) or ESA SCC 9000.  
Rev. E–20-Aug-01  
1

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