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MM74HCT164

更新时间： 2024-02-11 11:08:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器
页数 文件大小 规格书
6页 67K
描述
8-Bit Serial-in/Parallel-out Shift Register

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中文翻译

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MM74HCT164 技术参数

生命周期：Active包装说明：SOP-14
Reach Compliance Code：compliant风险等级：5.82
计数方向：RIGHT系列：HCT
JESD-30 代码：R-PDSO-G14长度：10.2 mm
负载电容（CL）：50 pF逻辑集成电路类型：SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup：25 Hz位数：8
功能数量：1端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
最大电源电流（ICC）：1.3 mA传播延迟（tpd）：38 ns
座面最大高度：2.1 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：5.3 mm
最小 fmax：35 MHz

MM74HCT164 数据手册

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February 1984  
Revised February 1999  
MM74HCT164  
8-Bit Serial-in/Parallel-out Shift Register  
The 74HCT logic family is functionally as well as pin-out  
compatible with the standard 74LS logic family. All inputs  
are protected from damage due to static discharge by inter-  
nal diode clamps to VCC and ground.  
General Description  
The MM74HCT164 utilizes advanced silicon-gate CMOS  
technology. It has the high noise immunity and low con-  
sumption of standard CMOS integrated circuits. It also  
offers speeds comparable to low power Schottky devices.  
MM74HCT devices are intended to interface between TTL  
and NMOS components and standard CMOS devices.  
These parts are also plug-in replacements for LS-TTL  
devices and can be used to reduce power consumption in  
existing designs.  
This 8-bit shift register has gated serial inputs and CLEAR.  
Each register bit is a D-type master/slave flip-flop. Inputs A  
& B permit complete control over the incoming data. A  
LOW at either or both inputs inhibits entry of new data and  
resets the first flip-flop to the low level at the next clock  
pulse. A HIGH level on one input enables the other input  
which will then determine the state of the first flip-flop. Data  
at the serial inputs may be changed while the clock is HIGH  
or LOW, but only information meeting the setup and hold  
time requirements will be entered. Data is serially shifted in  
and out of the 8-bit register during the positive going transi-  
tion of the clock pulse. Clear is independent of the clock  
and accomplished by a low level at the CLEAR input.  
Features  
■ Typical propagation delay: 20 ns  
■ Low quiescent current: 40 µA maximum (74HCT Series)  
■ Low input current: 1 µA maximum  
■ Fanout of 10 LS-TTL loads  
■ TTL input compatible  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HCT164M  
MM74HCT164SJ  
MM74HCT164N  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP) JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Truth Table  
Pin Assignments for DIP, SOIC and SOP  
Inputs  
Outputs  
QB ...  
Clear  
Clock  
A
B
QA  
QH  
L
X
L
↑
↑
↑
X
X
H
L
X
X
H
X
L
L
L
L
H
H
H
H
QAO QBO  
QHO  
QGn  
QGn  
QGn  
H
L
L
QAn  
QAn  
QAn  
X
H = HIGH Level (steady state)  
L = LOW Level (steady state)  
X = Irrelevant (any input, including transitions)  
↑ = Transition from LOW-to-HIGH level.  
Q
, Q , Q  
= the level of Q , Q , or Q , respectively, before the  
AO  
BO  
HO A B H  
indicated steady state input conditions were established.  
, Q = The level of Q or Q before the most recent ↑ transition of  
Q
An  
Gn  
A
G
the clock; indicated a one-bit shift.  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005765.prf  
www.fairchildsemi.com  
123456

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 		Serial In Parallel Out, HCT Series, 8-Bit, Right Direction, True Output, CMOS, PDSO14, 0.1
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 		HCT SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14, PLASTI

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