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MM74HC151N_NL

更新时间: 2024-09-28 13:11:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 复用器
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7页 74K
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MM74HC151N_NL 数据手册

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September 1983  
Revised February 1999  
MM74HC151  
8-Channel Digital Multiplexer  
The 74HC logic family is functionally as well as pin-out  
compatible with the standard 74LS logic family. All inputs  
are protected from damage due to static discharge by inter-  
nal diode clamps to VCC and ground.  
General Description  
The MM74HC151 high speed Digital multiplexer utilizes  
advanced silicon-gate CMOS technology. Along with the  
high noise immunity and low power dissipation of standard  
CMOS integrated circuits, it possesses the ability to drive  
10 LS-TTL loads. The MM74HC151 selects one of the 8  
data sources, depending on the address presented on the  
A, B, and C inputs. It features both true (Y) and comple-  
ment (W) outputs. The STROBE input must be at a low  
logic level to enable this multiplexer. A high logic level at  
the STROBE forces the W output HIGH and the Y output  
LOW.  
Features  
Typical propagation delay data select to output Y: 26 ns  
Wide operating supply voltage range: 2–6V  
Low input current: 1 µA maximum  
Low quiescent supply current: 80 µA maximum (74HC)  
High output drive current: 4 mA minimum  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HC151M  
MM74HC151SJ  
MM74HC151MTC  
MM74HC151N  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Truth Table  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Inputs  
Outputs  
Select  
Strobe  
C
X
L
B
X
L
A
X
L
S
H
L
L
L
L
L
L
L
L
Y
W
L
H
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
H = HIGH Level, L = LOW Level, X = Don't Care  
D0, D1...D7 = the level of the respective D input  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005313.prf  
www.fairchildsemi.com  

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