Datasheet > MM74C574SJX

MM74C574SJX

更新时间： 2024-09-27 20:04:27

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
7页	89K
描述
Bus Driver, CMOS Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, EIAJ TYPE2, SOP-20

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技术参数
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MM74C574SJX 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	20
Reach Compliance Code：	unknown	风险等级：	5.84
系列：	CMOS	JESD-30 代码：	R-PDSO-G20
长度：	12.6 mm	逻辑集成电路类型：	BUS DRIVER
位数：	8	功能数量：	1
端口数量：	2	端子数量：	20
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
传播延迟（tpd）：	194 ns	认证状态：	Not Qualified
座面最大高度：	2.1 mm	最大供电电压 (Vsup)：	6 V
最小供电电压 (Vsup)：	2 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	5.3 mm
Base Number Matches：	1

MM74C574SJX 数据手册

September 1983

Revised February 1999

MM74HC574

3-STATE Octal D-Type Edge-Triggered Flip-Flop

signals are present at the other inputs and the state of the

storage elements.

General Description

The MM74HC574 high speed octal D-type flip-flops utilize

advanced silicon-gate P-well CMOS technology. They pos-

sess the high noise immunity and low power consumption

of standard CMOS integrated circuits, as well as the ability

to drive 15 LS-TTL loads. Due to the large output drive

capability and the 3-STATE feature, these devices are ide-

ally suited for interfacing with bus lines in a bus organized

system.

The 74HC logic family is speed, function, and pinout com-

patible with the standard 74LS logic family. All inputs are

protected from damage due to static discharge by internal

diode clamps to V_CCand ground.

Features

■ Typical propagation delay: 18 ns

These devices are positive edge triggered flip-flops. Data

at the D inputs, meeting the set-up and hold time require-

ments, are transferred to the Q outputs on positive going

transitions of the CLOCK (CK) input. When a high logic

level is applied to the OUTPUT CONTROL (OC) input, all

outputs go to a high impedance state, regardless of what

■ Wide operating voltage range: 2V–6V

■ Low input current: 1 µA maximum

■ Low quiescent current: 80 µA maximum

■ Compatible with bus-oriented systems

■ Output drive capability: 15 LS-TTL loads

Ordering Code:

Order Number Package Number

Package Description

MM74C574WM

MM74C574SJ

MM74C574MTC

MM74C574N

M20B

M20D

MTC20

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300”

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4m Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Truth Table

Pin Assignments for DIP, SOIC, SOP and TSSOP

Output

Clock Data Output

Control

↑

Q₀

H = HIGH Level

L = LOW Level

X = Don't Care

↑ = Transition from LOW-to-HIGH

Z = High Impedance State

= The level of the output before steady state input conditions were

established

Top View

DS005213.prf

www.fairchildsemi.com

12 3 4 5 6 7

中文翻译

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与MM74C574SJX相关器件

型号	品牌	获取价格	描述	数据表
MM74C574WM	FAIRCHILD	获取价格	3-STATE Octal D-Type Edge-Triggered Flip-Flop
MM74C574WMX	FAIRCHILD	获取价格	Bus Driver, CMOS Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, MS-013, SOI
MM74C73	FAIRCHILD	获取价格	Dual J-K Flip-Flops with Clear and Preset
MM74C73_04	FAIRCHILD	获取价格	Dual J-K Flip-Flops with Clear and Preset
MM74C73J	TI	获取价格	IC CMOS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14,
MM74C73J/A+	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,CMOS,DIP,14PIN,CERAMIC
MM74C73N	FAIRCHILD	获取价格	Dual J-K Flip-Flops with Clear and Preset
MM74C73N	TI	获取价格	CMOS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, PLA
MM74C73N	ROCHESTER	获取价格	J-K Flip-Flop, CMOS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output,
MM74C73N/A+	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,CMOS,DIP,14PIN,PLASTIC

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