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MM74C32_04 PDF预览

MM74C32_04

更新时间: 2024-10-02 04:39:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
3页 40K
描述
Quad 2-Input OR Gate

MM74C32_04 数据手册

 浏览型号MM74C32_04的Datasheet PDF文件第2页浏览型号MM74C32_04的Datasheet PDF文件第3页 
October 1987  
Revised January 2004  
MM74C32  
Quad 2-Input OR Gate  
General Description  
Features  
The MM74C32 employs complementary MOS (CMOS)  
transistors to achieve low power and high noise margin,  
these gates provide the basic functions used in the imple-  
mentation of digital integrated circuit systems. The N- and  
P-channel enhancement mode transistors provide a sym-  
metrical circuit with output swings essentially equal to the  
supply voltage. This results in high noise immunity over a  
wide supply voltage range. No DC power other than that  
caused by leakage current is consumed during static con-  
ditions. All inputs are protected against static discharge  
damage.  
Wide supply voltage range: 3.0V to 15V  
Guaranteed noise margin: 1.0V  
High noise immunity: 0.45V VCC (typ.)  
Low power TTL compatibility: fan out of 2 driving 74L  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74C32N  
N14A  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Connection Diagram  
Top View  
© 2004 Fairchild Semiconductor Corporation  
DS005881  
www.fairchildsemi.com  

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