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ML7021MB PDF预览

ML7021MB

更新时间: 2024-01-06 07:39:55
品牌 Logo 应用领域
冲电气 - OKI 电信综合业务数字网光电二极管电信集成电路
页数 文件大小 规格书
24页 244K
描述
ISDN Echo Canceller, 1-Func, CMOS, PDSO28, 0.485 INCH, 0.65 MM PITCH, PLASTIC, SSOP-28

ML7021MB 技术参数

生命周期:Transferred零件包装代码:SSOP
包装说明:SSOP,针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.32JESD-30 代码:R-PDSO-G28
长度:10.5 mm功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH认证状态:Not Qualified
座面最大高度:2.25 mm标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:ISDN ECHO CANCELLER温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:9.5 mm
Base Number Matches:1

ML7021MB 数据手册

 浏览型号ML7021MB的Datasheet PDF文件第2页浏览型号ML7021MB的Datasheet PDF文件第3页浏览型号ML7021MB的Datasheet PDF文件第4页浏览型号ML7021MB的Datasheet PDF文件第6页浏览型号ML7021MB的Datasheet PDF文件第7页浏览型号ML7021MB的Datasheet PDF文件第8页 
¡ Semiconductor  
ML7021  
(2/4)  
Pin  
Symbol  
Type  
Description  
Control for the ATT function.  
5
ATT  
I
This pin prevents howling by attenuators (ATT) for the RIN input and SOUT  
output.  
If there is input only to RIN, the ATT for the SOUT output is activated.  
If there is no input to SIN, or if there is input to both SIN and RIN, the ATT  
for the RIN input is activated.  
Either the ATT for the RIN output or the ATT for the SOUT is always  
activated in all cases, and the attenuation of ATT is 6 dB.  
• Single Chip or Master Chip in a Cascade Connection  
"H": ATT OFF  
"L": ATT ON  
"L" is recommended if performing echo cancellation.  
• Slave Chip in a Cascade Connection  
Fixed at "L"  
This input signal is loaded in synchronization with the falling edge of the  
INT signal or the rising edge of the RST signal.  
6
INT  
I
Interrupt signal which starts 1 cycle (8 kHz) of the signal processing.  
Signal processing starts when "H"-to-"L" transition is detected.  
• Single Chip or Master Chip in a Cascade Connection  
Connect the IRLD pin.  
• Slave Chip in a Cascade Connection  
Connect the IRLD pin of the master chip.  
INT input is invalid for 100 ms after reset due to initialization.  
Refer to the control pin connection example.  
Load detection signal output when the SIN and RIN serial input data is  
loaded in the internal registers.  
7
IRLD  
O
• Single Chip  
Connect to the INT pin.  
• Master Chip in a Cascade Connection  
Connect to the INT pin of the master chip and all the slave chips.  
• Slave Chip in a Cascade Connection  
Leave open.  
Refer to the control pin connection example.  
8
9
SIN  
RIN  
SCK  
I
I
I
Transmit serial data.  
Input the PCM signal synchronized to SYNC and SCK. Data is read in at  
the falling edge of SCK.  
Receive serial data.  
Input the PCM signal synchronized to SYNC and SCK. Data is read in at  
the falling edge of SCK.  
10  
Clock input for transmit/receive serial data.  
This pin uses the external SCK or the SCKO.  
Input the PCM CODEC transmit/receive clock (64 to 2048 kHz).  
5

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