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ML4823 PDF预览

ML4823

更新时间: 2024-09-26 22:46:11
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 控制器
页数 文件大小 规格书
9页 123K
描述
High Frequency Power Supply Controller

ML4823 数据手册

 浏览型号ML4823的Datasheet PDF文件第2页浏览型号ML4823的Datasheet PDF文件第3页浏览型号ML4823的Datasheet PDF文件第4页浏览型号ML4823的Datasheet PDF文件第5页浏览型号ML4823的Datasheet PDF文件第6页浏览型号ML4823的Datasheet PDF文件第7页 
May 1997  
ML4823  
High Frequency Power Supply Controller  
FEATURES  
GENERAL DESCRIPTION  
Practical operation at switching frequencies to 1.0MHz  
High current (2A peak) totem pole output  
Wide bandwidth error amplifier  
The ML4823 High Frequency PWM Controller is an IC  
controller optimized for use in Switch Mode Power  
Supply designs running at frequencies to 1MHz.  
Propagation delays are minimal through the comparators  
and logic for reliable high frequency operation while slew  
rate and bandwidth are maximized on the error amplifier.  
This controller is designed for single-ended applications  
using voltage or current mode and provides for input  
voltage feed forward.  
Fully latched logic with double pulse suppression  
Pulse-by-pulse current limiting  
Soft start and max. duty cycle control  
Under voltage lockout with hysteresis  
5.1V trimmed bandgap reference  
A 1V threshold current limit comparator provides cycle-  
by-cycle current limit and exceeding a 1.4V threshold  
initiates a soft-start cycle. The soft start pin doubles as a  
maximum duty cycle clamp. All logic is fully latched to  
provide jitter-free operation and prevent multiple pulsing.  
An under-voltage lockout circuit with 800mV of hysteresis  
assures low startup current and drives the outputs low  
during fault conditions.  
Low start-up current (1.1mA)  
Pin compatible improved replacement for UC3823  
Fast shut down path from current limit to output  
Soft start latch ensures full soft start cycle  
Outputs pull low for undervoltage lockout  
This controller is an improved second source for the  
UC3823 controller; however, the ML4823 includes  
features not found on the 3823. These features are set in  
italics.  
BLOCK DIAGRAM (Pin Configuration Shown for 16-Pin Version)  
R
T
5
6
CLOCK OUT  
OSC  
4
C
T
R
S
1.25V  
+
RAMP  
7
3
+
Q
COMP  
E/A OUT  
NI  
2
1
+
ERROR  
AMP  
V+  
POWER V  
C
13  
14  
12  
INV  
OUTPUT  
SOFT START  
POWER GND  
8
+
4V  
+
I
I
REF  
LIM  
11  
9
1V  
+
/S.D.  
LIM  
ENABLE  
REF  
V
5.1V V  
REF  
5.1V  
16  
R
V
GEN  
REF  
Q
INTERNAL  
BIAS  
9V  
V
CC  
+
+
15  
10  
S
1.4V  
UNDER  
VOLTAGE  
LOCKOUT  
SIGNAL GND  
REV. 1.0 10/12/2000  

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