ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
MODE CONTROL LOGIC (V
SS
to V = 4.75 V to 12.6 V, T = – 40 to + 85°C)
DD A
Characteristic
Min
Typ
—
Max
V – 4.0
DD
Unit
V
V
V
Voltage for TTL Mode (TTL Logic Levels Referenced to V
)
LS
V
SS
LS
Voltage for CMOS Mode (CMOS Logic Levels of V
SS
to V
)
V
V
– 0.5
—
V
V
LS
DD
DD
DD
Mu/A Select Voltage
Mu–Law Mode
V
– 0.5
– 0.5
—
—
—
V
DD
DD
Sign Magnitude Mode
A–Law Mode
V
AG
V
+ 0.5
+ 0.5
AG
V
SS
V
SS
RSI Voltage for Reference Select Input (ML145502)
3.78 V Mode
2.5 V Mode
3.15 V Mode
V
– 0.5
– 0.5
—
—
—
V
V
V
DD
DD
V
AG
V
+ 0.5
+ 0.5
AG
V
SS
V
SS
V
ref
Voltage for Internal or External Reference (ML145502 Only)
Internal Reference Mode
External Reference Mode
V
—
—
V
V
+ 0.5
– 1.0
SS
+ 0.5
SS
DD
V
AG
Analog Test Mode Frequency, MS = CCI (ML145502 Only)
See Pin Description; Test Modes
—
128
—
kHz
SWITCHING CHARACTERISTICS (V
SS
to V
DD
= 9.5 V to 12.6 V, T = – 40 to + 85°C, C = 150 pF, CMOS or TTL Mode)
A
L
Characteristic
Symbol
Min
Typ
Max
Unit
Output Rise Time
Output Fall Time
TDD
t
t
—
—
30
30
80
80
ns
TLH
THL
Input Rise Time
Input Fall Time
TDE, TDC, RCE, RDC, DC, MSI, CCI
t
t
—
—
—
—
4
4
µs
TLH
THL
Pulse Width
TDE Low, TDC, RCE, RDC, DC, MSI, CCI
t
100
64
—
—
—
ns
w
DCLK Pulse Frequency (ML145502/05 Only)
CCI Clock Pulse Frequency (MSI = 8 kHz)
CCI is internally tied to TDC on the ML145503, therefore, the
transmit data clock must be one of these frequencies. This pin will accept
one of these discrete clock frequencies and will compensate to produce
internal sequencing.
TDC, RDC, DC
f
4096
kHz
kHz
CL
f
f
f
f
f
—
—
—
—
—
128
—
—
—
—
—
CL1
CL2
CL3
CL4
CL5
1536
1544
2048
2560
Propagation Delay Time
ns
TDE Rising to TDD Low Impedance
TTL
CMOS
TTL
CMOS
TTL
CMOS
TTL
CMOS
t
t
t
t
—
—
—
—
—
—
—
—
90
90
—
—
90
90
90
90
180
150
55
P1
P2
P3
P4
TDE Falling to TDD High Impedance
40
TDC Rising Edge to TDD Data, During TDE High
TDE Rising Edge to TDD Data, During TDC High
180
150
180
150
TDC Falling Edge to TDE Rising Edge Setup Time
TDE Rising Edge to TDC Falling Edge Setup Time
t
20
100
20
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
µA
pF
µA
su1
su2
su8
su3
su4
su5
su6
su7
t
t
t
t
t
t
t
TDE Falling Edge to TDC Rising Edge to Preserve the Next TDD Data
RDC Falling Edge to RCE Rising Edge Setup Time
RCE Rising Edge to RDC Falling Edge Setup Time
RDD Valid to RDC Falling Edge Setup Time
—
—
20
—
—
100
60
—
—
—
—
CCI Falling Edge to MSI Rising Edge Setup Time
MSI Rising Edge to CCI Falling Edge Setup Time
RDD Hold Time from RDC Falling Edge
20
—
—
100
100
—
—
—
t
h
—
—
TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI Input Capacitance
TDE,TDC, RCE, RDC, RDD, DC, MSI, CCI Input Current
TDD Capacitance During High Impedance (TDE Low)
TDD Input Current During High Impedance (TDE Low)
—
10
10
15
10.0
—
0.01
12
0.1
—
—
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