MK74CB178
Early Buffalo™ Clock Driver
ICRO CLOC K
Description
Features
The MK74CB178 Early Buffalo™ is a monolithic high speed
clock driver which is ideal for Pentium™, 486, and RISC
processor systems. It consists of three clock drivers capable of
accepting different inputs to produce one, seven and eight low-
skew, non-inverting outputs. The single input/output can be
used to maintain timing with the early CPU clock. When
combined with MicroClock’s MK14xx series of low jitter
clock synthesizers, the two chips form an unequaled high
performance clocking scheme for new processors. This is the
only solution on the market that meets Intel’s specs for skew
and jitter.
• Tiny 28 pin SSOP (150 mil) package
• Single input to single output for early clock
• Single input to seven output for CPU
• Single input to eight output for PCI
• Like outputs are skew matched to within 250ps
• A, B, and C outputs matched to 500ps
• 3.3V±10% and/or 5V±10% supply voltage
• Output Enable tri-states A clock outputs
• Each side (A, B+C) of eight clock drivers can run
from different supply voltages, making it possible
to have 3.3V and 5V amplitude clock outputs
from the same chip
Many new Pentium systems require multiple outputs for CPU
and PCI clocks, plus an early CPU clock for the core logic.
This monolithic solution eliminates any concern for part-to-
part skew matching. The MK74CB178 is packaged in the tiny
28 pin SSOP, which uses the same board space as the narrow
16 pin SOIC. An added feature of the chip is the ability to
produce both 3.3V and 5V amplitude clocks by connecting 5V
to VDDA and 3.3V to VDDBC. See MAN03 for dual voltage
operation.
• Clock speeds up to 66.67 MHz
Family of MicroClock Parts
The MK74CB178 Early Buffalo™ is designed to
be used with MicroClock’s clock synthesizer
devices, which will produce the CPU, memory,
and local bus clocks. MicroClock also makes the
MK74CB216, which is a dual one-to-eight buffer.
Consult MicroClock for applications support.
The MK74CB178 is also useful for Intel’s Triton chipset,
since the C input can be used to delay the PCI clock by 5ns
maximum (at 5V) before driving the A input.
VDDA
VDDBC
Block Diagram
INB
QB0
QB1
INA
QA0
QA1
QA2
QA3
QA4
QA5
QA6
QA7
QB2
QB3
QB4
QB5
QB6
QC0
INC
GNDA
GNDBC
OEA (all A clock outputs)
MDS74CB178B
1
Revision 4265
Printed 7/23/97
MicroClock Division of ICS•1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax