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MK1726-01AG PDF预览

MK1726-01AG

更新时间: 2024-02-06 17:34:06
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
8页 168K
描述
Clock Generator, 32MHz, CMOS, PDSO8, TSSOP-8

MK1726-01AG 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:SOIC
包装说明:TSSOP, TSSOP8,.25针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.49
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.4 mm端子数量:8
最高工作温度:85 °C最低工作温度:
最大输出时钟频率:32 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
主时钟/晶体标称频率:32 MHz认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Clock Generators
最大压摆率:35 mA最大供电电压:3.63 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

MK1726-01AG 数据手册

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MK1726A  
Low EMI Clock Generator  
Description  
Features  
The MK1726-01A/-02A/-04A devices generate a low  
EMI output clock from a clock or crystal input. The part  
is designed to dither the LCD interface clock for PDAs,  
printers, scanners, modems, copiers, etc. Using ICS’  
proprietary mix of analog and digital Phase Locked  
Loop (PLL) technology, the device spreads the  
frequency spectrum of the output and reduces the  
frequency amplitude peaks by several dB. The  
MK1726-01A/-02A/-04A devices offer both centered  
and down spread from a high-speed clock input.  
Packaged in 8-pin SOIC/TSSOP  
Provides a spread spectrum output clock  
Supports flat panel controllers  
Accepts a clock or crystal input (provides same  
frequency dithered output)  
Input frequency range of 4 to 32 MHz.  
Output frequency range of 4 to 128 MHz  
1X, 2X, 4X frequency multiplication  
1X: MK1726-01A; 2X: MK1726-02A; 4X:  
ICS offers many other clocks for computers and  
computer peripherals. Consult ICS when you need to  
remove crystals and oscillators from your board.  
MK1726-04A  
Center and down spread  
Peak reduction by 8 dB to 16 dB typical on 3rd  
through 19th odd harmonics  
Low EMI feature can be disabled  
Includes power down  
Operating voltage of 3.3 V  
Advanced, low-power CMOS process  
Block Diagram  
VDD  
2
S1:0  
PLL Clock  
Synthesis  
and Spread  
Spectrum  
Circuitry  
Spread Direction  
FRSEL  
SSCLK  
X1= 01A  
X2= 02A  
X4= 04A  
X1/CLK  
Clock Buffer/  
Crystal  
Ocsillator  
X2  
GND  
The crystal requires external capacitors  
for accurate tuning of the clock  
MDS 1726A B  
1
Revision 101703  
Integrated Circuit Systems, Inc. z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com  

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