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MK1726-01ASLFTR PDF预览

MK1726-01ASLFTR

更新时间: 2024-11-20 20:01:11
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
7页 173K
描述
Clock Generator, 32MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8

MK1726-01ASLFTR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.32JESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
湿度敏感等级:1端子数量:8
最高工作温度:85 °C最低工作温度:
最大输出时钟频率:32 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
主时钟/晶体标称频率:32 MHz认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Clock Generators
最大压摆率:35 mA最大供电电压:3.63 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL EXTENDED端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

MK1726-01ASLFTR 数据手册

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DATASHEET  
LOW EMI CLOCK GENERATOR  
MK1726-01A  
Description  
Features  
The MK1726-01A generates a low EMI output clock from a  
clock or crystal input. The part is designed to dither the LCD  
interface clock for PDAs, printers, scanners, modems,  
copiers, and others. Using IDT’s proprietary mix of analog  
and digital Phase-Locked Loop (PLL) technology, the  
device spreads the frequency spectrum of the output,  
reducing the frequency amplitude peaks by several dB. The  
MK1726-01A offers both centered and down spread from a  
high-speed clock input.  
Packaged in 8-pin SOIC  
Provides a spread spectrum output clock  
Supports flat panel controllers  
Accepts a clock or crystal input (provides same  
frequency dithered output)  
Input frequency range of 4 to 32 MHz  
Output frequency range of 4 to 32 MHz  
Center and down spread  
IDT offers many other clocks for computers and computer  
peripherals. Consult us when you need to remove crystals  
and oscillators from your board.  
Peak reduction by 8 dB to 16 dB typical on 3rd through  
19th odd harmonics  
Low EMI feature can be disabled  
Includes power down  
Operating voltage of 3.3 V  
Advanced, low-power CMOS process  
Block Diagram  
VDD  
2
S1:0  
Spread Direction  
FRSEL  
PLL Clock  
Synthesis  
and Spread  
Spectrum  
Circuitry  
SSCLK  
X1/CLK  
X1  
Clock Buffer/  
Crystal  
Ocsillator  
X2  
External caps required for with crystal  
for accurate tuning of the clock  
GND  
IDT™ / ICS™ LOW EMI CLOCK GENERATOR  
1
MK1726-01A REV D 071207  

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