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MH8S64DBKG-7 PDF预览

MH8S64DBKG-7

更新时间: 2024-09-29 22:27:43
品牌 Logo 应用领域
三菱 - MITSUBISHI 动态存储器
页数 文件大小 规格书
55页 683K
描述
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

MH8S64DBKG-7 数据手册

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Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64DBKG -7,-7L,-8,-8L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
DESCRIPTION  
Utilizes industry standard 4M x 16 Sy nchronous DRAMs  
The MH8S64DBKG is 8388608 - word by 64-bit  
Synchronous DRAM module. This consists of eight  
industry standard 4Mx16 Synchronous DRAMs in  
TSOP and one industory standard EEPROM in  
TSSOP.  
TSOP and industry standard EEPROM in TSSOP  
144-pin (72-pin dual in-line package)  
single 3.3V±0.3V power supply  
The mounting of TSOP on a card edge Dual  
Inline package provides any application where  
high densities and large quantities of memory are  
required.  
Clock frequency 100MHz(max.)  
Fully synchronous operation referenced to clock rising  
edge  
This is a socket type - memory modules, suitable  
for easy interchange or addition of modules.  
4 bank operation controlled by BA0,1(Bank Address)  
/CAS latency- 2/3(programmable)  
Burst length- 1/2/4/8/Full Page(programmable)  
Burst type- sequential / interleave(programmable)  
Column access - random  
FEATURES  
CLK Access Time  
Frequency  
(Component SDRAM)  
6.0ns(CL=2)  
6.0ns(CL=3)  
-7,-7L  
-8,-8L  
100MHz  
100MHz  
Auto precharge / All bank precharge controlled by A10  
Auto refresh and Self refresh  
4096 refresh cycle /64ms  
LVTTL Interface  
PC100 compliant  
APPLICATION  
main memory or graphic memory in computer systems  
PCB Outline  
(Front)  
(Back)  
1
2
143  
144  
MITSUBISHI  
MIT-DS-0340-0.0  
17.Sep.1999  
ELECTRIC  
( 1 / 55 )  

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