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MG-7010SA

更新时间： 2024-10-02 03:49:35
品牌 Logo 应用领域
爱普生 - EPSON 振荡器输出元件
页数 文件大小 规格书
2页 82K
描述
SELECTABLE-OUTPUT PLL OSCILLATOR

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中文翻译

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MG-7010SA 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.91
JESD-609代码：e0振荡器类型：CMOS
端子面层：Tin/Lead (Sn/Pb)Base Number Matches：1

MG-7010SA 数据手册

 浏览型号MG-7010SA的Datasheet PDF文件第2页 
Crystal oscillator  
SELECTABLE-OUTPUT PLL OSCILLATOR  
MG-7010SA  
• Can output one CPU frequency among 15 selections.  
• Reflow able, high-density mounting-type SMD.  
• Provided with output enable and stand-by function to allow  
low current consumption.  
• Using C-MOS IC allows low current consumption and  
assures high reliability.  
Actual size  
Specifications (characteristics)  
Item  
Frequency change time  
Symbol  
ft  
Specifications  
10ms max.  
Remark  
S0, S1, S2, S3 changing  
VDD=4.5V to 5.5V  
t
20.0000 MHz to 120.0000 MHz  
20.0000 MHz to 80.0000 MHz  
-0.5V to +7.0V  
Output frequency range  
f0  
VDD=2.7V to 5.5V  
Max. supply voltage  
VDD-GND  
VDD  
Power source  
voltage  
Operating voltage  
Storage temperature  
Operating temperature  
2.7V to 5.5V  
-55˚C to +100˚C  
-10˚C to +70˚C  
TSTG  
TOPR  
TSOL  
∆f / f0  
lop  
Stored as bare product after unpacking  
Temperature  
range  
Soldering condition  
Frequency stability  
Current consumption  
Output disable current  
Standby current  
Twice at under 260˚C within 10 sec. or under 230˚C within 3 min.  
C: ±100ppm  
45mA max.  
-10˚C to +70˚C, VDD=2.7V to 5.5V  
No load condition (fo=120 MHz)  
OE=GND, fo=120 MHz  
IOE  
25mA max.  
_
IST  
10µA max.  
ST=GND  
Duty  
tw/t  
40% to 60%  
1.4V level  
High output voltage  
Low output voltage  
VOH  
VOL  
VDD -0.5V min.  
0.4V max.  
25pF max.  
IOH = -16mA (VDD=5±0.5V)  
IOL = 16mA (VDD=5±0.5V)  
VDD=4.5V to 5.5V( f0 ≤ 80 MHz)  
Output load condition  
CL  
15pF max.  
VDD=2.7V to 4.5V or f0 > 80 MHz  
_
High input voltage  
Low input voltage  
Output rise time  
Output fall time  
Oscillation start up time  
Aging  
VIH  
VIL  
tTLH  
tTHL  
tOSC  
fa  
2.0V min.  
0.8V max.  
ST,OE terminal  
_
ST,OE terminal  
20%→80%VDD level  
4.0ns max.  
4.0ns max.  
10ms max.  
±5ppm/year max.  
80%→20%VDD level  
Time at 4.5V to be 0 sec.  
Ta=25˚C, VDD =3.3V or 5.5V  
Three drops on a hard board from 75 cm or  
excitation test with 3000g x 0.3ms 1/2 sine wave in 3 directions  
Shock resistance  
S.R.  
±20ppm max.  
Output frequency  
Output frequency (MHz)  
Select bit  
100.0  
33.33  
30.0  
120.0  
25.0  
20.0  
70.0  
80.0  
75.0  
66.66  
60.0  
60.0  
50.0  
45.0  
90.0  
40.0  
S3  
S2  
S1  
S0  
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
External dimensions  
(Unit: mm)  
Terminal connection  
Terminal  
No.  
Terminal  
symbol  
Function  
1
2
4
5
S3  
GND  
S0  
Frequency select bit 3  
Ground  
Frequency select bit 0  
Frequency select bit 1  
Output Enable control  
Clock out at “ H ”  
high-impedance at “L”  
M7010 C  
E 935 6A  
S1  
6
7
OE  
__  
ST  
Stand by control  
“H”→ Clock out  
“L”→ “Level”  
10.1±0.2  
0˚ to  
10˚  
Power supply  
Clock output  
8
13  
14  
VDD  
OUT  
S2  
Frequency select bit 2  
0.05 min.  
0.15  
3, 9, 10  
11, 12  
0.6  
No connection  
N.C  
46  
12

中文翻译

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